Cypress CY7C1429BV18, CY7C1423BV18, CY7C1424BV18 manual Switching Waveforms, NOP Read Write, Burst

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CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [27, 28, 29]

NOP

READ

READ

WRITE

WRITE

READ

NOP

 

 

(burst of 2)

(burst of 2)

(burst of 2)

(burst of 2)

(burst of 2)

 

 

1

2

3

4

5

6

7

8

K

K

LD

R/W

A

D

Q

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKH

 

tKL

 

tCYC

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSC

 

A0

 

A1

A2

 

A3

 

A4

 

 

t

SA

t

HA

 

tHD

 

 

tHD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSD

 

 

tSD

 

 

 

 

 

 

 

 

D20

D21

D30

D31

 

 

 

 

 

Q00

Q01

Q10

Q11

 

Q40

Q41

 

 

 

t KHCH

tCLZ

tCQD

tDOH

 

 

 

 

 

 

 

 

 

 

 

tKHCH

 

 

 

tCO

tCQDOH

 

 

tCHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C#

CQ

CQ#

tCQOH

tCQOH

tCCQO

tKH

 

tKL

tCCQO

tCQH

tCYC

tCQHCQH

tKHKH

DON’T CARE

UNDEFINED

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document #: 001-07035 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideCLK Logic Block Diagram CY7C1422BV18Doff Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1424BV18 1M x CY7C1423BV18 2M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleWrite Cycle Descriptions Truth TableLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW DLL Timing Static to DLL ResetNOP Read Write Switching WaveformsBurst Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History REV ECN no Submission ORIG. Description of Change Date