Cypress CY7C1423BV18 Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1422BV18 4M x

Page 4

CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Pin Configuration

The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1422BV18 (4M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

CQ

NC/72M

A

R/W

NWS1

K

NC/144M

LD

A

A

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1429BV18 (4M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

CQ

NC/72M

A

R/W

NC

K

NC/144M

LD

A

A

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document #: 001-07035 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideCLK Logic Block Diagram CY7C1422BV18Doff Logic Block Diagram CY7C1423BV18 Logic Block Diagram CY7C1424BV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1423BV18 2M x CY7C1424BV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Echo ClocksTruth Table Write Cycle DescriptionsLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW Static to DLL Reset DLL TimingNOP Read Write Switching WaveformsBurst Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no Submission ORIG. Description of Change Date