Cypress CY7C1424BV18, CY7C1423BV18, CY7C1429BV18, CY7C1422BV18 manual Capacitance, Thermal Resistance

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CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

 

 

 

 

 

 

CIN

Input Capacitance

TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V

5

pF

CCLK

Clock Input Capacitance

 

4

pF

CO

Output Capacitance

 

5

pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

 

Test Conditions

165 FBGA

Unit

 

Package

 

 

 

 

 

ΘJA

Thermal Resistance

 

Test conditions follow standard test methods and

17.2

°C/W

 

(Junction to Ambient)

 

procedures for measuring thermal impedance, in

 

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

 

3.2

°C/W

 

 

 

(Junction to Case)

 

 

 

 

 

 

Figure 4. AC Test Loads and Waveforms

 

 

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES[20]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

20.Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.

Document #: 001-07035 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideCLK Logic Block Diagram CY7C1422BV18Doff Logic Block Diagram CY7C1423BV18 Logic Block Diagram CY7C1424BV18CY7C1422BV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1429BV18 4M xCY7C1423BV18 2M x CY7C1424BV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Application Example Echo ClocksLD R/W Truth TableWrite Cycle Descriptions BWS0/ BWS1 NWS0 NWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW Static to DLL Reset DLL TimingNOP Read Write Switching WaveformsBurst Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no Submission ORIG. Description of Change Date