Cypress CY7C1429BV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 17

CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Identification Register Definitions

Instruction Field

Value

CY7C1422BV18

CY7C1429BV18

CY7C1423BV18

CY7C1424BV18

Description

Revision Number	000	000	000	000	Version number.
(31:29)

Cypress Device ID	11010100010000111	11010100010001111	11010100010010111	11010100010100111	Defines the type of
(28:12)					SRAM.
Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
(11:1)					identification of
					SRAM vendor.
ID Register	1	1	1	1	Indicates the
Presence (0)					presence of an ID
					register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

ID

Boundary Scan

3

1

32

109

Instruction Codes

Instruction

Code

Description

EXTEST	000	Captures the input and output ring contents.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document #: 001-07035 Rev. *D

Page 17 of 30

[+] Feedback

Image 17

Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1422BV18CLK Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1424BV18 1M x CY7C1423BV18 2M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleWrite Cycle Descriptions Truth TableLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitLOW Switching CharacteristicsHigh DLL Timing Static to DLL ResetBurst Switching WaveformsNOP Read Write Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History REV ECN no Submission ORIG. Description of Change Date