CY7C1422BV18, CY7C1429BV18
CY7C1423BV18, CY7C1424BV18
Logic Block Diagram (CY7C1423BV18)
D[17:0]
20
A(19:0)
K
K
DOFF
R/W
VREF
LD
BWS[1:0]
18 |
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|
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| Write | Write |
Address |
| Data Reg | Data Reg |
Write Add. Decode |
|
| |
Register | 1M x 18 Array | 1M x 18 Array | |
CLK | |||
Gen. |
Read Data Reg.
|
| 36 |
| 18 | |
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Control |
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|
| 18 | |
Logic |
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Read Add. Decode
Reg.
Reg.
LD
Control R/W
Logic
C
C
|
| CQ |
Reg. 18 |
| CQ |
|
| |
18 | 18 | Q[17:0] |
Logic Block Diagram (CY7C1424BV18)
D[35:0]
19
A(18:0)
K
K
DOFF
R/W
VREF
LD
BWS[3:0]
36 |
|
|
| |
|
| Write | Write | |
Address |
| Data Reg | Data Reg | |
Decode | 512K x | 512K x | ||
Register | ||||
| ||||
CLK | Write Add. | 36 Array | 36 Array | |
Gen. |
Read Data Reg.
|
| 72 |
| 36 | |
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| |||
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| |
Control |
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|
| 36 | |
Logic |
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| ||
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Read Add. Decode
Reg.
Reg.
LD
Control R/W
Logic
C
C
|
| CQ |
Reg. 36 |
| CQ |
|
| |
36 | 36 | Q[35:0] |
Document #: | Page 3 of 30 |
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