Cypress CY7C1429BV18, CY7C1423BV18, CY7C1424BV18, CY7C1422BV18 Application Example, Echo Clocks

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CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Echo Clocks

DLL

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 23.

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note AN5062, DLL Considerations in QDRII/DDRII/QDRII+/DDRII+.

Application Example

Figure 1 shows four DDR-II SIO used in an application.

Figure 1. Application Example

 

DATA IN

 

DATA OUT

 

Address

 

LD#

 

R/W#

BUS

BWS#

 

MASTER

SRAM 1 Input CQ

(CPU

SRAM 1 Input CQ#

or

SRAM 4 Input CQ

SRAM 4 Input CQ#

ASIC)

 

 

Source K

 

Source K#

 

Delayed K

 

Delayed K#

 

 

 

SRAM 1

 

 

 

ZQ

 

 

SRAM 4

 

 

 

ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

Q

R = 250Ohms

 

 

B

 

 

 

Q

Vt

 

 

 

 

 

 

CQ

 

 

 

 

 

CQ

 

 

 

W

 

 

 

 

 

 

W

 

 

 

 

D

LD R/W

B

 

 

 

CQ#

D

LD R/W

 

 

 

CQ#

 

S

 

 

 

S

 

 

 

R

A

LD R/W W

 

 

 

 

A

#

#

#

 

 

 

 

#

#

#

C

C#

K

K#

C

C#

K

K#

 

 

#

#

#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

R

R = 50Ohms

Vt = VREF

 

 

 

 

 

 

 

 

 

 

 

 

R = 250Ohms

Document #: 001-07035 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1422BV18 CLKDoff Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1424BV18 1M x CY7C1423BV18 2M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleWrite Cycle Descriptions Truth TableLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW DLL Timing Static to DLL ResetSwitching Waveforms NOP Read WriteBurst Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History REV ECN no Submission ORIG. Description of Change Date