Cypress CY7C6435x, CY7C64345 manual Register Map Bank 0 Table User Space, Name Addr 0,Hex Access

CY7C6431x

CY7C64345, CY7C6435x

Table 5. Register Map Bank 0 Table: User Space

Name	Addr (0,Hex)	Access	Name	Addr (0,Hex)	Access	Name	Addr (0,Hex)	Access	Name	Addr (0,Hex)	Access
PRT0DR	00	RW	EP1_CNT0	40	#		80			C0
PRT0IE	01	RW	EP1_CNT1	41	RW		81			C1
	02		EP2_CNT0	42	#		82			C2
	03		EP2_CNT1	43	RW		83			C3
PRT1DR	04	RW	EP3_CNT0	44	#		84			C4
PRT1IE	05	RW	EP3_CNT1	45	RW		85			C5
	06		EP4_CNT0	46	#		86			C6
	07		EP4_CNT1	47	RW		87			C7
PRT2DR	08	RW	EP5_CNT0	48	#		88		I2C_XCFG	C8	RW
PRT2IE	09	RW	EP5_CNT1	49	RW		89		I2C_XSTAT	C9	R
	0A		EP6_CNT0	4A	#		8A		I2C_ADDR	CA	RW
	0B		EP6_CNT1	4B	RW		8B		I2C_BP	CB	R
PRT3DR	0C	RW	EP7_CNT0	4C	#		8C		I2C_CP	CC	R
PRT3IE	0D	RW	EP7_CNT1	4D	RW		8D		CPU_BP	CD	RW
	0E		EP8_CNT0	4E	#		8E		CPU_CP	CE	R
	0F		EP8_CNT1	4F	RW		8F		I2C_BUF	CF	RW
PRT4DR	10	RW		50			90		CUR_PP	D0	RW
PRT4IE	11	RW		51			91		STK_PP	D1	RW
	12			52			92			D2
	13			53			93		IDX_PP	D3	RW
	14			54			94		MVR_PP	D4	RW
	15			55			95		MVW_PP	D5	RW
	16			56			96		I2C_CFG	D6	RW
	17			57			97		I2C_SCR	D7	#
	18		PMA0_DR	58	RW		98		I2C_DR	D8	RW
	19		PMA1_DR	59	RW		99			D9
	1A		PMA2_DR	5A	RW		9A		INT_CLR0	DA	RW
	1B		PMA3_DR	5B	RW		9B		INT_CLR1	DB	RW
	1C		PMA4_DR	5C	RW		9C		INT_CLR2	DC	RW
	1D		PMA5_DR	5D	RW		9D		INT_CLR3	DD	RW
	1E		PMA6_DR	5E	RW		9E		INT_MSK2	DE	RW
	1F		PMA7_DR	5F	RW		9F		INT_MSK1	DF	RW
	20			60			A0		INT_MSK0	E0	RW
	21			61			A1		INT_SW_EN	E1	RW
	22			62			A2		INT_VC	E2	RC
	23			63			A3		RES_WDT	E3	W
	24		PMA8_DR	64	RW		A4		INT_MSK3	E4	RW
	25		PMA9_DR	65	RW		A5			E5
	26		PMA10_DR	66	RW		A6			E6
	27		PMA11_DR	67	RW		A7			E7
	28		PMA12_DR	68	RW		A8			E8
SPI_TXR	29	W	PMA13_DR	69	RW		A9			E9
SPI_RXR	2A	R	PMA14_DR	6A	RW		AA			EA
SPI_CR	2B	#	PMA15_DR	6B	RW		AB			EB
	2C		TMP_DR0	6C	RW		AC			EC
	2D		TMP_DR1	6D	RW		AD			ED
	2E		TMP_DR2	6E	RW		AE			EE
	2F		TMP_DR3	6F	RW		AF			EF
	30			70		PT0_CFG	B0	RW		F0
USB_SOF0	31	R		71		PT0_DATA1	B1	RW		F1
USB_SOF1	32	R		72		PT0_DATA0	B2	RW		F2
USB_CR0	33	RW		73		PT1_CFG	B3	RW		F3
USBIO_CR0	34	#		74		PT1_DATA1	B4	RW		F4
USBIO_CR1	35	#		75		PT1_DATA0	B5	RW		F5
EP0_CR	36	#		76		PT2_CFG	B6	RW		F6
EP0_CNT0	37	#		77		PT2_DATA1	B7	RW	CPU_F	F7	RL
EP0_DR0	38	RW		78		PT2_DATA0	B8	RW		F8
EP0_DR1	39	RW		79			B9			F9
EP0_DR2	3A	RW		7A			BA			FA
EP0_DR3	3B	RW		7B			BB			FB
EP0_DR4	3C	RW		7C			BC			FC
EP0_DR5	3D	RW		7D			BD			FD
EP0_DR6	3E	RW		7E			BE		CPU_SCR1	FE	#
EP0_DR7	3F	RW		7F			BF		CPU_SCR0	FF	#
Gray fields are reserved; do not access			these fields.	# Access is bit	specific.
Document Number: 001-12394 Rev *G										Page 11 of 28

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