Cypress CY7C64345 manual Register Map Bank 1 Table Configuration Space, Name Addr 1,Hex Access

Page 12

CY7C6431x

CY7C64345, CY7C6435x

Table 6. Register Map Bank 1 Table: Configuration Space

Name

Addr (1,Hex)

Access

Name

 

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

PRT0DM0

00

RW

PMA4_RA

 

40

RW

 

80

 

 

C0

 

PRT0DM1

01

RW

PMA5_RA

 

41

RW

 

81

 

 

C1

 

 

02

 

PMA6_RA

 

42

RW

 

82

 

 

C2

 

 

03

 

PMA7_RA

 

43

RW

 

83

 

 

C3

 

PRT1DM0

04

RW

PMA8_WA

 

44

RW

 

84

 

 

C4

 

PRT1DM1

05

RW

PMA9_WA

 

45

RW

 

85

 

 

C5

 

 

06

 

PMA10_WA

 

46

RW

 

86

 

 

C6

 

 

07

 

PMA11_WA

 

47

RW

 

87

 

 

C7

 

PRT2DM0

08

RW

PMA12_WA

 

48

RW

 

88

 

 

C8

 

PRT2DM1

09

RW

PMA13_WA

 

49

RW

 

89

 

 

C9

 

 

0A

 

PMA14_WA

 

4A

RW

 

8A

 

 

CA

 

 

0B

 

PMA15_WA

 

4B

RW

 

8B

 

 

CB

 

PRT3DM0

0C

RW

PMA8_RA

 

4C

RW

 

8C

 

 

CC

 

PRT3DM1

0D

RW

PMA9_RA

 

4D

RW

 

8D

 

 

CD

 

 

0E

 

PMA10_RA

 

4E

RW

 

8E

 

 

CE

 

 

0F

 

PMA11_RA

 

4F

RW

 

8F

 

 

CF

 

PRT4DM0

10

RW

PMA12_RA

 

50

RW

 

90

 

 

D0

 

PRT4DM1

11

RW

PMA13_RA

 

51

RW

 

91

 

 

D1

 

 

12

 

PMA14_RA

 

52

RW

 

92

 

 

D2

 

 

13

 

PMA15_RA

 

53

RW

 

93

 

 

D3

 

 

14

 

EP1_CR0

 

54

#

 

94

 

 

D4

 

 

15

 

EP2_CR0

 

55

#

 

95

 

 

D5

 

 

16

 

EP3_CR0

 

56

#

 

96

 

 

D6

 

 

17

 

EP4_CR0

 

57

#

 

97

 

 

D7

 

 

18

 

EP5_CR0

 

58

#

 

98

 

 

D8

 

 

19

 

EP6_CRO

 

59

#

 

99

 

 

D9

 

 

1A

 

EP7_CR0

 

5A

#

 

9A

 

 

DA

 

 

1B

 

EP8_CR0

 

5B

#

 

9B

 

 

DB

 

 

1C

 

 

 

5C

 

 

9C

 

IO_CFG

DC

RW

 

1D

 

 

 

5D

 

 

9D

 

OUT_P1

DD

RW

 

1E

 

 

 

5E

 

 

9E

 

 

DE

 

 

1F

 

 

 

5F

 

 

9F

 

 

DF

 

 

20

 

 

 

60

 

 

A0

 

OSC_CR0

E0

RW

 

21

 

 

 

61

 

 

A1

 

ECO_CFG

E1

#

 

22

 

 

 

62

 

 

A2

 

OSC_CR2

E2

RW

 

23

 

 

 

63

 

 

A3

 

VLT_CR

E3

RW

 

24

 

 

 

64

 

 

A4

 

VLT_CMP

E4

R

 

25

 

 

 

65

 

 

A5

 

 

E5

 

 

26

 

 

 

66

 

 

A6

 

 

E6

 

 

27

 

 

 

67

 

 

A7

 

 

E7

 

 

28

 

 

 

68

 

 

A8

 

IMO_TR

E8

W

SPI_CFG

29

RW

 

 

69

 

 

A9

 

ILO_TR

E9

W

 

2A

 

 

 

6A

 

 

AA

 

 

EA

 

 

2B

 

 

 

6B

 

 

AB

 

SLP_CFG

EB

RW

 

2C

 

TMP_DR0

 

6C

RW

 

AC

 

SLP_CFG2

EC

RW

 

2D

 

TMP_DR1

 

6D

RW

 

AD

 

SLP_CFG3

ED

RW

 

2E

 

TMP_DR2

 

6E

RW

 

AE

 

 

EE

 

 

2F

 

TMP_DR3

 

6F

RW

 

AF

 

 

EF

 

USB_CR1

30

#

 

 

70

 

 

B0

 

 

F0

 

 

31

 

 

 

71

 

 

B1

 

 

F1

 

 

32

 

 

 

72

 

 

B2

 

 

F2

 

USBIO_CR2

33

RW

 

 

73

 

 

B3

 

 

F3

 

PMA0_WA

34

RW

 

 

74

 

 

B4

 

 

F4

 

PMA1_WA

35

RW

 

 

75

 

 

B5

 

 

F5

 

PMA2_WA

36

RW

 

 

76

 

 

B6

 

 

F6

 

PMA3_WA

37

RW

 

 

77

 

 

B7

 

CPU_F

F7

RL

PMA4_WA

38

RW

 

 

78

 

 

B8

 

 

F8

 

PMA5_WA

39

RW

 

 

79

 

 

B9

 

 

F9

 

PMA6_WA

3A

RW

 

 

7A

 

 

BA

 

 

FA

 

PMA7_WA

3B

RW

 

 

7B

 

 

BB

 

 

FB

 

PMA0_RA

3C

RW

 

 

7C

 

 

BC

 

 

FC

 

PMA1_RA

3D

RW

 

 

7D

 

 

BD

 

 

FD

 

PMA2_RA

3E

RW

 

 

7E

 

 

BE

 

 

FE

 

PMA3_RA

3F

RW

 

 

7F

 

 

BF

 

 

FF

 

Gray fields are

reserved; do not access these fields.

#

Access is bit specific.

 

 

 

 

 

 

Document Number: 001-12394 Rev *G

 

 

 

 

 

 

 

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Contents Features EnCoRe V Block DiagramCypress Semiconductor Corporation 198 Champion Court Functional Overview Getting StartedEnCoRe V Core Additional System ResourcesDevelopment Tools PSoC Designer Software SubsystemsConfigure Components Designing with PSoC DesignerSelect Components Generate, Verify, and DebugDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPin Configuration Pin Part PinoutPin Part Pinout QFN Pin No Type Name Description QFN CY7C64355/CY7C64356 48-Pin enCoRe V USB Device Pin Part Pinout QFN Pin No Type Pin Name DescriptionCY7C6431x Register Reference Register ConventionsRegister Mapping Tables Register Conventions DescriptionName Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessElectrical Specifications Units of Measure Symbol Unit of MeasureADC Electrical Specifications INLElectrical Characteristics DC Electrical CharacteristicsDC Chip Level Specifications Absolute Maximum RatingsDC General Purpose IO Specifications DC POR and LVD Specifications AC Electrical Characteristics DC Programming SpecificationsAC Chip Level Specifications 160 175 AC General Purpose I/O Specifications AC External Clock SpecificationsAC Programming Specifications AC SPI SpecificationsAC SPI Specifications Symbol Description Min Typ Max Units AC I2C Specifications Definition of Timing for Fast/Standard Mode on the I2C BusPackage Diagram Packaging DimensionsPin 5 x 5 x 0.55 mm QFN Package Handling Pin 7 x 7 x 0.9 mm QFNSolder Reflow Peak Temperature Thermal ImpedancesOrdering Information Document History TYJ/ARISales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions