Cypress CY7C6431x manual Designing with PSoC Designer, Select Components, Configure Components

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CY7C6431x CY7C64345, CY7C6435x

Designing with PSoC Designer

The development process for the enCoRe V device differs from that of a traditional fixed function microprocessor. Powerful PSoC Designer tools get the core of your design up and running in minutes instead of hours.

The development process can be summarized in the following four steps:

1.Select Components

2.Configure Components

3.Organize and Connect

4.Generate, Verify, and Debug

Select Components

The chip-level view provides a library of pre-built, pre-tested hardware peripheral components. These components are called “user modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed-signal varieties.

Configure Components

Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application.

The chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide perfor- mance specifications. Each data sheet describes the use of each user module parameter and contains other information you may need to successfully implement your design.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.

Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.

A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.

The last step in the development process takes place inside PSoC Designer’s Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

Organize and Connect

You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. In the chip-level view, you perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

Document Number: 001-12394 Rev *G

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Contents EnCoRe V Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court Functional Overview Getting StartedEnCoRe V Core Additional System ResourcesDevelopment Tools PSoC Designer Software SubsystemsConfigure Components Designing with PSoC DesignerSelect Components Generate, Verify, and DebugDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPin Part Pinout Pin ConfigurationPin Part Pinout QFN Pin No Type Name Description QFN CY7C64355/CY7C64356 48-Pin enCoRe V USB Device Pin Part Pinout QFN Pin No Type Pin Name DescriptionCY7C6431x Register Reference Register ConventionsRegister Mapping Tables Register Conventions DescriptionName Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessElectrical Specifications Units of Measure Symbol Unit of MeasureADC Electrical Specifications INLElectrical Characteristics DC Electrical CharacteristicsDC Chip Level Specifications Absolute Maximum RatingsDC General Purpose IO Specifications DC POR and LVD Specifications DC Programming Specifications AC Electrical CharacteristicsAC Chip Level Specifications 160 175 AC General Purpose I/O Specifications AC External Clock SpecificationsAC SPI Specifications AC Programming SpecificationsAC SPI Specifications Symbol Description Min Typ Max Units AC I2C Specifications Definition of Timing for Fast/Standard Mode on the I2C BusPackage Diagram Packaging DimensionsPin 5 x 5 x 0.55 mm QFN Package Handling Pin 7 x 7 x 0.9 mm QFNThermal Impedances Solder Reflow Peak TemperatureOrdering Information Document History TYJ/ARISales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions