Cypress CY7C6431x, CY7C64345, CY7C6435x manual Qfn

CY7C6431x

CY7C64345, CY7C6435x

32-Pin Part Pinout

Figure 2. CY7C64343/CY7C64345 32-Pin enCoRe V USB Device

P0[1]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

32 Vss

1

2

3

4

5

6

7

8 9

Vss

P0[3]	P0[5]	P0[7]	Vdd	P0[6]	P0[4]
31	30	29	28	27	26

QFN

( Top View)

10	11	12	13	14	15
D+	D–	Vdd	P1[0]	P1[2]	P1[4]

25 P0[2]

24 P0[0]

23 P2[6]

22 P2[4]

21 P2[2]

20 P2[0]

19 P3[2]

18 P3[0]

16	17	XRES
P1[6]

Table 2. 32-Pin Part Pinout (QFN)
Pin No.	Type	Name	Description
1	IOH	P0[1]	Digital I/O
2	I/O	P2[5]	Digital I/O, Crystal Output (Xout)
3	I/O	P2[3]	Digital I/O, Crystal Input (Xin)
4	I/O	P2[1]	Digital I/O
5	IOHR	P1[7]	Digital I/O, I2C SCL, SPI SS
6	IOHR	P1[5]	Digital I/O, I2C SDA, SPI MISO
7	IOHR	P1[3]	Digital I/O, SPI CLK
8	IOHR	P1[1](1, 2)	Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
9	Power	Vss	Ground
10	I/O	D+	USB PHY
11	I/O	D–	USB PHY
12	Power	Vdd	Supply voltage
13	IOHR	P1[0](1, 2)	Digital I/O, ISSP DATA, I2C SDA, SPI CLK
14	IOHR	P1[2]	Digital I/O
15	IOHR	P1[4]	Digital I/O, optional external clock input (EXTCLK)
16	IOHR	P1[6]	Digital I/O
17	Reset	XRES	Active high external reset with internal pull down
18	I/O	P3[0]	Digital I/O
19	I/O	P3[2]	Digital I/O
20	I/O	P2[0]	Digital I/O
21	I/O	P2[2]	Digital I/O
22	I/O	P2[4]	Digital I/O
23	I/O	P2[6]	Digital I/O
24	IOH	P0[0]	Digital I/O
25	IOH	P0[2]	Digital I/O
26	IOH	P0[4]	Digital I/O
27	IOH	P0[6]	Digital I/O
28	Power	Vdd	Supply voltage
29	IOH	P0[7]	Digital I/O
30	IOH	P0[5]	Digital I/O
31	IOH	P0[3]	Digital I/O
32	Power	Vss	Ground
CP	Power	Vss	Ensure the center pad is connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12394 Rev *G			Page 7 of 28

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