Cypress CY14B104N, CY14B104L manual Package Diagrams, Pin Tsop II

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CY14B104L, CY14B104N

Package Diagrams

DIMENSION IN MM (INCH)

MAX

MIN.

O R E

K X A

S G

EJECTOR PIN

0° -5°

0.10 (.004)

18.517 (0.729)

18.313 (0.721)

10.262 (0.404)

10.058 (0.396)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

51-85087-*A

Document #: 001-07102 Rev. *L

Page 19 of 25

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionTsop PinoutsTop View Not to scalePin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A07 Mode PowerNoise Considerations Mode Selection A15 A07 PowerPreventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Read Cycle AC Switching CharacteristicsSwitching Waveforms Min MaxCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 Parameters Description CY14B104L/CY14B104N Unit Min Max AutoStore/Power Up RecallHSB Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Pulse Width Hardware Store CycleHardware Store LOW to Store Busy 500 Truth Table For Sram Operations Inputs/Outputs2 Mode PowerHigh Z Ordering Information CY14B104L-BA45XIT CY14B104L-ZS45XCTCY14B104L-ZS45XIT CY14B104L-BA45XCTNvsram Part Numbering NomenclatureCY 14 B 104 L ZS P 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 UHA Document HistoryTUP PCIGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information