Cypress CY14B104N, CY14B104L manual Software Controlled STORE/RECALL Cycle

Page 13

CY14B104L, CY14B104N

Software Controlled STORE/RECALL Cycle

In the following table, the software controlled STORE/RECALL cycle parameters are listed.[25, 26]

Parameters

Description

 

20 ns

 

25 ns

 

45 ns

Unit

Min

Max

Min

Max

Min

Max

 

 

 

tRC

STORE/RECALL Initiation Cycle Time

20

 

25

 

45

 

ns

tSA

Address Setup Time

0

 

0

 

0

 

ns

tCW

Clock Pulse Width

15

 

20

 

30

 

ns

tHA

Address Hold Time

0

 

0

 

0

 

ns

tRECALL

RECALL Duration

 

200

 

200

 

200

μs

tSS [27, 28]

Soft Sequence Processing Time

 

100

 

100

 

100

μs

Switching Waveforms

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[26]

 

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5:,

 

 

 

Figure 13. Autostore Enable / Disable Cycle

 

W5&

W5&

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5:,

 

 

Notes

25.The software sequence is clocked with CE controlled or OE controlled reads.

26.The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. After the sixth address read cycle, no further read or write operation must be performed for tSS duration. If these conditions are not met, the software sequence is aborted.

Document #: 001-07102 Rev. *L

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale TsopPin Definitions Sram Read Device OperationSram Write AutoStore OperationMode Selection Hardware Recall Power UpA15 A07 Mode Power Software StorePreventing AutoStore Mode Selection A15 A07 PowerData Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsMin Max Sram Read CycleCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 Parameters Description CY14B104L/CY14B104N Unit Min Max AutoStore/Power Up RecallHSB Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Pulse Width Hardware Store CycleHardware Store LOW to Store Busy 500 Truth Table For Sram Operations Inputs/Outputs2 Mode PowerHigh Z Ordering Information CY14B104L-ZS45XIT CY14B104L-ZS45XCTCY14B104L-BA45XCT CY14B104L-BA45XITCY 14 B 104 L ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 TUP Document HistoryPCI UHAGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information