Cypress CY14B104N, CY14B104L manual Gvch/Pyrs

Page 23

CY14B104L, CY14B104N

Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM

Document Number: 001-07102

Rev.

ECN No.

Submission

Orig. of

 

 

 

 

Description of Change

Date

Change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*F

1889928

See ECN

vsutmp8/AE-

Added Footnotes 1, 2 and 3.

 

 

 

SA

Updated logic block diagram

 

 

 

 

Added 48-FBGA (X8) Pin Diagram

 

 

 

 

Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8).

 

 

 

 

Updated pin definitions table.

 

 

 

 

Corrected typo in VIL min spec

 

 

 

 

Changed the value of ICC3 from 25mA to 13mA

 

 

 

 

Changed ISB value from 1mA to 2mA

 

 

 

 

Rearranging of Footnotes.

 

 

 

 

Updated ordering information table

 

 

 

 

 

 

 

 

 

*G

2267286

See ECN

GVCH/PYRS

Added

BHE

and

BLE

Information in Pin Definitions Table

 

 

 

 

Updated Figure 4 (Autostore mode)

 

 

 

 

Updated footnote 6

 

 

 

 

Changed ICC2 & ICC4 from 3 mA to 6 mA

 

 

 

 

Changed ICC3 from 13 mA to 15 mA

 

 

 

 

Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max

 

 

 

 

value

 

 

 

 

Changed ISB from 2 mA to 3 mA

 

 

 

 

 

 

Added input leakage current (IIX) for HSB in DC Electrical Characteristics table

 

 

 

 

Corrected typo in tDBE value from 22 ns to 20 ns for 45 ns part

 

 

 

 

Corrected typo in tHZBE value from 22 ns to 15 ns for 45 ns part

 

 

 

 

Corrected typo in tAW value from 15 ns to 10ns for 15 ns part

 

 

 

 

Changed tRECALL from 100 to 200 us

 

 

 

 

Added footnotes 9 and 25; Reframed footnote 14 and 21

 

 

 

 

Added footnote 14 to figure 7 (SRAM WRITE Cycle #1)

 

 

 

 

 

*H

2483627

See ECN

GVCH/PYRS

Removed 8 mA typical ICC at 200 ns cycle time in Feature section

 

 

 

 

Referenced footnote 8 to ICC3 in DC Characteristics table

 

 

 

 

Changed ICC3 from 15 mA to 35 mA

 

 

 

 

Changed Vcap minimum value from 54 uF to 61 uF

 

 

 

 

Changed tAVAV to tRC

 

 

 

 

Figure 11:Changed tSA to tAS and tSCE to tCW

*I

2519319

06/20/08

GVCH/PYRS

Added 20 ns access speed in “Features”

 

 

 

 

Added ICC1 for tRC=20 ns for both industrial and Commercial temperature

 

 

 

 

Grade

 

 

 

 

updated Thermal resistance table values for 48-FBGA, 44-TSOP II and

 

 

 

 

54-TSOP II Packages

 

 

 

 

Added AC Switching Characteristics specs for 20 ns access speed

 

 

 

 

Added software controlled STORE/RECALL cycle specs for 20 ns access

 

 

 

 

speed

 

 

 

 

Updated ordering information and part numbering nomenclature

 

 

 

 

 

 

 

 

 

 

 

Document #: 001-07102 Rev. *L

Page 23 of 25

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionTsop PinoutsTop View Not to scalePin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A07 Mode PowerNoise Considerations Mode Selection A15 A07 PowerPreventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Read Cycle AC Switching CharacteristicsSwitching Waveforms Min MaxCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 HSB AutoStore/Power Up RecallParameters Description CY14B104L/CY14B104N Unit Min Max Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store LOW to Store Busy 500 Hardware Store CycleHardware Store Pulse Width High Z Inputs/Outputs2 Mode PowerTruth Table For Sram Operations Ordering Information CY14B104L-BA45XIT CY14B104L-ZS45XCTCY14B104L-ZS45XIT CY14B104L-BA45XCTNvsram Part Numbering NomenclatureCY 14 B 104 L ZS P 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 UHA Document HistoryTUP PCIGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information