Cypress CY14B104N, CY14B104L manual Features, Functional Description, Logic Block Diagram1, 2

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CY14B104L, CY14B104N

4 Mbit (512K x 8/256K x 16) nvSRAM

Features

20 ns, 25 ns, and 45 ns Access Times

Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N)

Hands off Automatic STORE on power down with only a small Capacitor

STORE to QuantumTrap® nonvolatile elements initiated by software, device pin, or AutoStore® on power down

RECALL to SRAM initiated by software or power up

Infinite Read, Write, and Recall Cycles

200,000 STORE cycles to QuantumTrap

20 year data retention

Single 3V +20% to –10% operation

Commercial and Industrial Temperatures

48-ball FBGA and 44/54-pin TSOP II packages

Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

Logic Block Diagram[1, 2, 3]

 

 

 

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Notes

 

 

 

 

 

 

1.

Address A0 - A18 for x8 configuration and Address A0

- A17 for x16 configuration.

 

 

 

 

2.

Data DQ0

- DQ7 for x8 configuration and Data DQ0

- DQ15 for x16 configuration.

 

 

 

 

3.

BHE and

BLE are applicable for x16 configuration only.

 

 

 

 

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 001-07102 Rev. *L

 

 

 

Revised December 19, 2008

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale TsopPin Definitions Sram Read Device OperationSram Write AutoStore OperationMode Selection Hardware Recall Power UpA15 A07 Mode Power Software StorePreventing AutoStore Mode Selection A15 A07 PowerData Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsMin Max Sram Read CycleCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 Parameters Description CY14B104L/CY14B104N Unit Min Max AutoStore/Power Up RecallHSB Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Pulse Width Hardware Store CycleHardware Store LOW to Store Busy 500 Truth Table For Sram Operations Inputs/Outputs2 Mode PowerHigh Z Ordering Information CY14B104L-ZS45XIT CY14B104L-ZS45XCTCY14B104L-BA45XCT CY14B104L-BA45XITCY 14 B 104 L ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 TUP Document HistoryPCI UHAGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information