CY14B104L, CY14B104N
Table 1. Mode Selection (continued)
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| [3] | A15 - A0[7] | Mode | IO | Power |
| CE |
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| WE | OE, | BHE, | BLE | |||||||||
| L |
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| H |
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| L | 0x4E38 | Read SRAM | Output Data | Active[8, 9] | |||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x4B46 | AutoStore Enable | Output Data |
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| L |
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| H |
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| L | 0x4E38 | Read SRAM | Output Data | Active ICC2[8, 9] | |||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x8FC0 | Nonvolatile Store | Output High Z |
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| L |
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| H |
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| L | 0x4E38 | Read SRAM | Output Data | Active[8, 9] | |||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x4C63 | Nonvolatile | Output High Z |
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| Recall |
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Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed:
1.Read address 0x4E38 Valid READ
2.Read address 0xB1C7 Valid READ
3.Read address 0x83E0 Valid READ
4.Read address 0x7C1F Valid READ
5.Read address 0x703F Valid READ
6.Read address 0x8B45 AutoStore Disable
The AutoStore is
1.Read address 0x4E38 Valid READ
2.Read address 0xB1C7 Valid READ
3.Read address 0x83E0 Valid READ
4.Read address 0x7C1F Valid READ
5.Read address 0x703F Valid READ
6.Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or
Data Protection
The CY14B104L/CY14B104N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104L/CY14B104N is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Document #: | Page 6 of 25 |
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