Cypress CY14B104N, CY14B104L manual 51-85160

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CY14B104L, CY14B104N

Figure 18. 54-Pin TSOP II (51-85160)

Document #: 001-07102 Rev. *L

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale TsopPin Definitions Sram Read Device OperationSram Write AutoStore OperationMode Selection Hardware Recall Power UpA15 A07 Mode Power Software StorePreventing AutoStore Mode Selection A15 A07 PowerData Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsMin Max Sram Read CycleCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 AutoStore/Power Up Recall Parameters Description CY14B104L/CY14B104N Unit Min MaxHSB Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Cycle Hardware Store Pulse WidthHardware Store LOW to Store Busy 500 Inputs/Outputs2 Mode Power Truth Table For Sram OperationsHigh Z Ordering Information CY14B104L-ZS45XIT CY14B104L-ZS45XCTCY14B104L-BA45XCT CY14B104L-BA45XITCY 14 B 104 L ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 TUP Document HistoryPCI UHAGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information