Cypress CY14B104L, CY14B104N manual Document History, Tup, Pci, Uha

Page 22

CY14B104L, CY14B104N

Document History Page

Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM

Document Number: 001-07102

Rev.

ECN No.

Submission

Orig. of

Description of Change

Date

Change

 

 

 

 

 

 

 

 

 

 

 

 

**

431039

See ECN

TUP

New Data Sheet

 

 

 

 

 

*A

489096

See ECN

TUP

Removed 48 SSOP Package

 

 

 

 

Added 48 FBGA and 54 TSOPII Packages

 

 

 

 

Updated Part Numbering Nomenclature and Ordering Information

 

 

 

 

Added Soft Sequence Processing Time Waveform

 

 

 

 

 

*B

499597

See ECN

PCI

Removed 35 ns speed bin

 

 

 

 

Added 55 ns speed bin. Updated AC table for the same

 

 

 

 

Changed “Unlimited” read/write to “infinite” read/write

 

 

 

 

Features section: Changed typical ICC at 200-ns cycle time to 8 mA

 

 

 

 

Changed STORE cycles from 500K to 200K cycles

 

 

 

 

Shaded Commercial grade in operating range table

 

 

 

 

Modified Icc/Is specs

 

 

 

 

48 FBGA package nomenclature changed from BW to BV

 

 

 

 

Modified part nomenclature table. Changes reflected in ordering information

 

 

 

 

table

 

 

 

 

 

*C

517793

See ECN

TUP

Removed 55ns speed bin

 

 

 

 

Changed pinout for 44TSOPII and 54TSOPII packages

 

 

 

 

Changed ISB to 1mA

 

 

 

 

Changed ICC4 to 3mA

 

 

 

 

Changed VCAP min to 35μF

 

 

 

 

Changed VIH max to Vcc + 0.5V

 

 

 

 

Changed tSTORE to 15ms

 

 

 

 

Changed tPWE to 10ns

 

 

 

 

Changed tSCE to 15ns

 

 

 

 

Changed tSD to 5ns

 

 

 

 

Changed tAW to 10ns

 

 

 

 

Removed tHLBL

 

 

 

 

 

 

 

 

Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW

 

 

 

 

Removed min specification for Vswitch

 

 

 

 

Changed tGLAX to 1ns

 

 

 

 

Added tDELAY max of 70us

 

 

 

 

Changed tSS specification from 70us min to 70us max

*D

774001

See ECN

UHA

Changed the data sheet from Advance information to Preliminary

 

 

 

 

48 FBGA package code changed from BV to BA

 

 

 

 

Removed 48 FBGA package in X8 configuration in ordering information.

 

 

 

 

Changed tDBE to 10ns in 15ns part

 

 

 

 

Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns

 

 

 

 

Changed tBW in 15ns part to 15ns and in 25ns part to 20ns

 

 

 

 

Changed tGLAX to tGHAX

 

 

 

 

Changed the value of ICC3 to 25mA

 

 

 

 

Changed the value of tAW in 15ns part to15ns

 

 

 

 

Changed A18 and A19 Pins in FBGA Pin Configuration to NC

*E

914220

See ECN

UHA

Included all the information for 45 ns part in this data sheet

 

 

 

 

 

 

 

 

 

Document #: 001-07102 Rev. *L

Page 22 of 25

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Image 22
Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationNot to scale PinoutsTop View TsopPin Definitions Sram Write Device OperationSram Read AutoStore OperationA15 A07 Mode Power Hardware Recall Power UpMode Selection Software StoreData Protection Mode Selection A15 A07 PowerPreventing AutoStore Noise ConsiderationsOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsMin Max AC Switching CharacteristicsSwitching Waveforms Sram Read CycleCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 Parameters Description CY14B104L/CY14B104N Unit Min Max AutoStore/Power Up RecallHSB Software Controlled STORE/RECALL Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min MaxHardware Store Pulse Width Hardware Store CycleHardware Store LOW to Store Busy 500 Truth Table For Sram Operations Inputs/Outputs2 Mode PowerHigh Z Ordering Information CY14B104L-BA45XCT CY14B104L-ZS45XCTCY14B104L-ZS45XIT CY14B104L-BA45XITZS Tsop Part Numbering NomenclatureCY 14 B 104 L ZS P 20 X C T NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 PCI Document HistoryTUP UHAGVCH/PYRS Aesa GVCH/DSGSales, Solutions, and Legal Information USB