Cypress CY14B104N, CY14B104L manual Sram Write Cycle #2 CE Controlled 3, 17, 18

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		CY14B104L, CY14B104N
Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]
	tWC
Address	Address Valid
tSA	tSCE	tHA
CE
BHE, BLE	tBW
BHE, BLE
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
Data Output	High Impedance
Data Output
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19]
	W:&
$GGUHVV	$GGUHVV9DOLG
	W6&(
&(
W6$	W%:	W+$
%+(%/(
	W$:
	W3:(
:(
	W6'	W+'
'DWD,QSXW	,QSXW'DWD9DOLG
	+LJK,PSHGDQFH
'DWD2XWSXW

Document #: 001-07102 Rev. *L

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionTsop PinoutsTop View Not to scalePin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A07 Mode PowerNoise Considerations Mode Selection A15 A07 PowerPreventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Read Cycle AC Switching CharacteristicsSwitching Waveforms Min MaxCY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 HSB AutoStore/Power Up RecallParameters Description CY14B104L/CY14B104N Unit Min Max Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store LOW to Store Busy 500 Hardware Store CycleHardware Store Pulse Width High Z Inputs/Outputs2 Mode PowerTruth Table For Sram Operations Ordering Information CY14B104L-BA45XIT CY14B104L-ZS45XCTCY14B104L-ZS45XIT CY14B104L-BA45XCTNvsram Part Numbering NomenclatureCY 14 B 104 L ZS P 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 UHA Document HistoryTUP PCIGVCH/PYRS GVCH/DSG AesaUSB Sales, Solutions, and Legal Information

Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]