Cypress CY14B101LA, CY14B101NA manual AutoStore/Power Up Recall

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PRELIMINARY

CY14B101LA, CY14B101NA

AutoStore/Power Up RECALL

Parameters

Description

20 ns

25 ns

45 ns

Unit

Min

Max

Min

Max

Min

Max

tHRECALL [27]

Power Up RECALL Duration

20

20

20

ms

tSTORE [23]

STORE Cycle Duration

8

8

8

ms

tDELAY [24]

Time Allowed to Complete SRAM Cycle

20

25

25

ns

VSWITCH

Low Voltage Trigger Level

2.65

2.65

2.65

V

tVCCRISE

VCC Rise Time

150

150

150

µs

VHDIS[14]

HSB

Output Driver Disable Voltage

1.9

1.9

1.9

V

tLZHSB

HSB

To Output Active Time

5

5

5

µs

tHHHD

HSB

High Active Time

500

500

500

ns

Switching Waveforms

Figure 11. AutoStore or Power Up RECALL[27]

VSWITCH
VHDIS
VVCCRISE	Note23	t	Note23	t
		STORE		STORE
	tHHHD		tHHHD	Note26
	tHHHD		tHHHD
HSB OUT			tDELAY
			tDELAY
	tLZHSB		t
Autostore			LZHSB
Autostore
	tDELAY
POWER-
UP
RECALL	tHRECALL		tHRECALL
			tHRECALL

Read & Write

Inhibited

(RWI)

POWER-UP Read & Write	BROWN	POWER-UP	Read & Write	POWER
RECALL	OUT	RECALL		DOWN
	Autostore			Autostore

Notes

22.tHRECALL starts from the time VCC rises above VSWITCH.

23.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

24.On a Hardware STORE, Software STORE / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

25.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

26.HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-42879 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationPinouts Top ViewNot to scale Output Enable, Active LOW. The active LOW Byte High Enable, Active LOW. Controls DQ15 DQ8Byte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10%Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A09 Mode Power Software StoreMode Selection A15 A09 Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min MaxTo Output Active Time when write latch not set Hardware Store CycleDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse WidthTruth Table for x8 Configuration Inputs/Outputs Mode Power Truth Table for x16 ConfigurationInputs/Outputs Mode Power Truth Table For Sram OperationsOrdering Information CY14B101LA-ZS25XCT CY14B101LA-ZS25XCCY14B101LA-BA25XCT CY14B101LA-BA25XCCY14B101LA-ZS45XCT CY14B101LA-ZS45XCCY14B101LA-BA45XCT CY14B101LA-BA45XCPart Numbering Nomenclature CY 14 B 101L A-ZS 20 X C TZS Tsop NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic Document History UNC/PYRSGVCH/AESA GVCH/PYRSSales, Solutions, and Legal Information USB