Contents
Features
Logic Block Diagram1, 2
Functional Description
Cypress Semiconductor Corporation
Top View
Pinouts
Not to scale
Output Enable, Active LOW. The active LOW
Byte High Enable, Active LOW. Controls DQ15 DQ8
Byte Low Enable, Active LOW. Controls DQ7 DQ0
Power Supply Inputs to the Device .0V +20%, -10%
Device Operation
Sram Read
Sram Write
AutoStore Operation
Hardware Recall Power Up
Mode Selection
A15 A09 Mode Power
Software Store
Mode Selection A15 A09
Preventing AutoStore
Data Protection
Noise Considerations
DC Electrical Characteristics
Maximum Ratings
Operating Range
Range
Data Retention and Endurance
Capacitance
Thermal Resistance
AC Test Conditions
AC Switching Characteristics
Switching Waveforms
Parameters Sram Read Cycle
Sram Write Cycle
Sram Read Cycle #2 CE and OE Controlled 3, 15
Sram Write Cycle #2 CE Controlled 3, 18, 19
AutoStore/Power Up Recall
Parameters Description 20 ns 25 ns 45 ns Unit Min Max
Software Controlled STORE/RECALL Cycle
Description 20 ns 25 ns 45 ns Unit Min Max
To Output Active Time when write latch not set
Hardware Store Cycle
Description 20ns 25ns 45ns Unit Min Max
Hardware Store Pulse Width
Truth Table for x8 Configuration Inputs/Outputs Mode Power
Truth Table for x16 Configuration
Inputs/Outputs Mode Power
Truth Table For Sram Operations
Ordering Information
CY14B101LA-ZS25XCT
CY14B101LA-ZS25XC
CY14B101LA-BA25XCT
CY14B101LA-BA25XC
CY14B101LA-ZS45XCT
CY14B101LA-ZS45XC
CY14B101LA-BA45XCT
CY14B101LA-BA45XC
Part Numbering Nomenclature
CY 14 B 101L A-ZS 20 X C T
ZS Tsop
Nvsram
Package Diagrams
Pin Tsop II
Ball Fbga 6 mm x 10 mm x 1.2 mm
Pin Ssop
Pin Soic
Document History
UNC/PYRS
GVCH/AESA
GVCH/PYRS
Sales, Solutions, and Legal Information
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