Cypress CY14B101NA, CY14B101LA manual Features, Functional Description, Logic Block Diagram1, 2

PRELIMINARY CY14B101LA, CY14B101NA

1 Mbit (128K x 8/64K x 16) nvSRAM

Features

■20 ns, 25 ns, and 45 ns Access Times

■Internally organized as 128K x 8 (CY14B101LA) or 64K x 16 (CY14B101NA)

■Hands off Automatic STORE on power down with only a small Capacitor

■STORE to QuantumTrap® nonvolatile elements initiated by Software, device pin, or AutoStore® on power down

■RECALL to SRAM initiated by software or power up

■Infinite Read, Write, and Recall Cycles

■200,000 STORE cycles to QuantumTrap

■20 year data retention

■Single 3V +20% to -10% operation

■Commercial and Industrial Temperatures

■48-ball FBGA, 44-pin TSOP - II, 48-pin SSOP, and 32-pin SOIC packages

■Pb-free and RoHS compliance

Functional Description

The Cypress CY14B101LA/CY14B101NA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 128K bytes of 8 bits each or 64K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

Logic Block Diagram[1, 2, 3]

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Note
1.	Address A0 - A16 for x8 configuration and Address A0 - A15 for x16 configuration.
2.	Data DQ0	- DQ7 for x8 configuration and Data DQ0	- DQ15 for x16 configuration.
3.	BHE and	BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation			• 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-42879 Rev. *B					Revised January 29, 2009

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