Cypress CY14B101LA, CY14B101NA manual Data Retention and Endurance, Capacitance, Thermal Resistance

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PRELIMINARY

CY14B101LA, CY14B101NA

Data Retention and Endurance

Parameter

Description

Min

Unit

DATAR

Data Retention

20

Years

NVC

Nonvolatile STORE Operations

200

K

Capacitance

Parameter[14]

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

7

pF

VCC = 0 to 3.0V

COUT

Output Capacitance

7

pF

Thermal Resistance

Parameter[14]

Description

Test Conditions

48-FBGA

48-SSOP

44-TSOP II

32-SOIC

Unit

ΘJA

Thermal Resistance

Test conditions follow standard

28.82

TBD

31.11

TBD

°C/W

(Junction to Ambient)

test methods and procedures for

measuring thermal impedance,

ΘJC

Thermal Resistance

7.84

TBD

5.56

TBD

°C/W

in accordance with EIA/JESD51.

(Junction to Case)

Figure 5. AC Test Loads

	3.0V	577Ω
	3.0V	R1
		R1
	OUTPUT

30 pF

577Ω	for tri-state specs

3.0V

R1

OUTPUT

R2

5 pF

R2

789Ω

789Ω

AC Test Conditions

Input Pulse Levels	0V to 3V
Input Rise and Fall Times (10% - 90%)	<3 ns
Input and Output Timing Reference Levels	1.5V

Note

14. These parameters are guaranteed by design and are not tested.

Document #: 001-42879 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationNot to scale PinoutsTop View Output Enable, Active LOW. The active LOW Byte High Enable, Active LOW. Controls DQ15 DQ8Byte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10%Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A09 Mode Power Software StoreMode Selection A15 A09 Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min MaxTo Output Active Time when write latch not set Hardware Store CycleDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse WidthTruth Table for x8 Configuration Inputs/Outputs Mode Power Truth Table for x16 ConfigurationInputs/Outputs Mode Power Truth Table For Sram OperationsOrdering Information CY14B101LA-ZS25XCT CY14B101LA-ZS25XCCY14B101LA-BA25XCT CY14B101LA-BA25XCCY14B101LA-ZS45XCT CY14B101LA-ZS45XCCY14B101LA-BA45XCT CY14B101LA-BA45XCPart Numbering Nomenclature CY 14 B 101L A-ZS 20 X C TZS Tsop NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic Document History UNC/PYRSGVCH/AESA GVCH/PYRSSales, Solutions, and Legal Information USB