Cypress CY14B101NA, CY14B101LA Pin Definitions Pin Name Type Description, Hardware Store Busy

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PRELIMINARY

CY14B101LA, CY14B101NA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pinouts (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC

VCAP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

48

 

VCC

 

 

A16

 

 

 

 

 

 

 

 

2

 

 

 

47

 

A15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A14

 

3

 

 

 

46

 

HSB

 

 

 

 

 

 

 

 

 

 

A12

 

 

 

 

 

 

 

 

4

 

 

 

45

 

WE

 

 

 

 

A7

 

 

 

 

 

 

 

 

5

 

 

 

44

 

A13

 

 

A6

 

 

 

 

 

 

 

 

6

 

 

 

43

 

A8

 

 

A5

 

 

 

 

 

 

 

 

7

 

 

 

42

 

A9

 

 

 

 

 

 

 

 

 

INT

 

8

 

 

 

41

 

NC

 

 

 

 

 

 

 

 

 

A4

 

9

48-SSOP

40

 

A11

 

 

 

 

 

 

NC

 

 

 

 

10

39

 

NC

 

 

 

 

 

 

 

 

 

NC

 

11

Top View

38

 

NC

 

 

 

 

 

 

NC

 

 

12

37

 

NC

 

 

 

 

 

 

 

VSS

 

 

13

(not to scale)

36

 

V

 

 

 

 

 

 

NC

 

 

14

 

 

 

 

 

SS

 

 

 

 

 

 

 

35

 

NC

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

34

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ0

 

16

 

 

 

33

 

DQ6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

18

 

 

 

31

 

A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

19

 

 

 

 

 

 

 

 

 

 

 

30

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

20

 

 

 

29

 

DQ7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1

 

21

 

 

 

28

 

DQ5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ2

 

 

 

 

 

 

 

 

22

 

 

 

27

 

DQ4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

23

 

 

 

26

 

DQ3

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

24

 

 

 

25

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 1.

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

I/O Type

 

 

Description

 

A0 – A16

Input

Address Inputs Used to Select one of the 131,072 bytes of the nvSRAM for x8 Configuration.

A0 – A15

Address Inputs Used to Select one of the 65,536 words of the nvSRAM for x16 Configuration.

 

DQ0 – DQ7

Input/Output

Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.

DQ – DQ

Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on

0

 

 

 

 

 

 

15

 

operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

Input

Write Enable Input, Active LOW. When the chip is enabled and

WE

is LOW, data on the I/O pins is written

 

 

 

 

 

 

 

 

 

 

 

 

 

to the specific address location.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Input

Output Enable, Active LOW. The active LOW

OE

input enables the data output buffers during read

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cycles. I/O pins are tri-stated on deasserting OE HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Byte High Enable, Active LOW. Controls DQ15 - DQ8.

 

 

 

BHE

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Byte Low Enable, Active LOW. Controls DQ7 - DQ0.

 

 

 

BLE

 

 

 

 

VSS

 

Ground

Ground for the Device. Must be connected to the ground of the system.

 

 

 

VCC

 

Power

Power Supply Inputs to the Device. 3.0V +20%, –10%

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply

 

 

 

 

 

 

 

 

 

 

 

 

 

[8]

Input/Output

Hardware STORE Busy

(HSB)

. When LOW this output indicates that a Hardware STORE is in progress.

 

HSB

 

 

 

 

 

 

 

 

 

 

 

 

 

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up

 

 

 

 

 

 

 

 

 

 

 

 

 

resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is

 

 

 

 

 

 

 

 

 

 

 

 

 

driven HIGH for short time with standard output high current.

 

 

 

 

 

 

 

VCAP

 

Power

AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to

 

 

 

 

 

 

 

 

 

 

 

 

Supply

nonvolatile elements.

 

 

 

 

NC

 

No Connect

No Connect. This pin is not connected to the die.

 

 

 

 

 

Document #: 001-42879 Rev. *B

Page 3 of 25

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionPinouts Top ViewNot to scale Power Supply Inputs to the Device .0V +20%, -10% Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 DQ8 Byte Low Enable, Active LOW. Controls DQ7 DQ0AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A09 Mode PowerNoise Considerations Mode Selection A15 A09Preventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallDescription 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20ns 25ns 45ns Unit Min MaxTruth Table For Sram Operations Truth Table for x8 Configuration Inputs/Outputs Mode PowerTruth Table for x16 Configuration Inputs/Outputs Mode PowerOrdering Information CY14B101LA-BA25XC CY14B101LA-ZS25XCTCY14B101LA-ZS25XC CY14B101LA-BA25XCTCY14B101LA-BA45XC CY14B101LA-ZS45XCTCY14B101LA-ZS45XC CY14B101LA-BA45XCTNvsram Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic GVCH/PYRS Document HistoryUNC/PYRS GVCH/AESAUSB Sales, Solutions, and Legal Information