Cypress CY14B101NA, CY14B101LA manual Ball Fbga 6 mm x 10 mm x 1.2 mm

Page 21

PRELIMINARY CY14B101LA, CY14B101NA

Package Diagrams (continued)

Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)

TOP VIEW

A1 CORNER

1 2 3 4 5 6

BOTTOM VIEW

A1 CORNER

Ø0.05 M C

 

 

 

 

Ø0.25 M C A B

 

 

 

Ø0.30±0.05(48X)

 

 

 

6

5

4

3

2

1

 

 

A

 

 

B

 

 

10.00±0.10

C

D

 

 

 

 

E

 

 

F

 

 

G

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

0.53±0.05

 

 

 

 

 

0.25 C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.36

6.00±0.10

0.21±0.05

 

 

 

 

 

 

 

 

 

0.15 C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEATING PLANE

C

1.20 MAX

10.00±0.10

A

 

 

A

 

 

B

 

0.75

C

5.25

D

E

 

 

 

2.625

F

 

G

 

 

 

 

H

 

 

1.875

 

 

0.75

 

 

3.75

 

B

6.00±0.10

 

0.15(4X)

 

 

 

51-85128-*D

Document #: 001-42879 Rev. *B

Page 21 of 25

[+] Feedback

Image 21
Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationPinouts Top ViewNot to scale Byte High Enable, Active LOW. Controls DQ15 DQ8 Output Enable, Active LOW. The active LOWByte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10%Sram Read Device OperationSram Write AutoStore OperationMode Selection Hardware Recall Power UpA15 A09 Mode Power Software StorePreventing AutoStore Mode Selection A15 A09Data Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallDescription 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Cycle To Output Active Time when write latch not setDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse WidthTruth Table for x16 Configuration Truth Table for x8 Configuration Inputs/Outputs Mode PowerInputs/Outputs Mode Power Truth Table For Sram OperationsOrdering Information CY14B101LA-ZS25XC CY14B101LA-ZS25XCTCY14B101LA-BA25XCT CY14B101LA-BA25XCCY14B101LA-ZS45XC CY14B101LA-ZS45XCTCY14B101LA-BA45XCT CY14B101LA-BA45XCCY 14 B 101L A-ZS 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic UNC/PYRS Document HistoryGVCH/AESA GVCH/PYRSUSB Sales, Solutions, and Legal Information