Cypress CY14B101LA, CY14B101NA manual Hardware Store Cycle, Description 20ns 25ns 45ns Unit Min Max

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PRELIMINARY CY14B101LA, CY14B101NA

Hardware STORE Cycle

Parameters

Description

20ns

25ns

45ns

Unit

Min

Max

Min

Max

Min

Max

tDHSB

HSB

To Output Active Time when write latch not set

20

25

25

ns

tPHSB

Hardware STORE Pulse Width

15

15

15

ns

tSS [29, 30]

Soft Sequence Processing Time

100

100

100

μs

Switching Waveforms

Figure 14. Hardware STORE Cycle[23]

Write latch set

HSB (IN)

HSB (OUT)

DQ (Data Out)

RWI

tPHSB

tDELAY

tSTORE

tHHHD

tLZHSB

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

tDELAY

tDHSB

HSB pin is driven high to VCC only by Internal 100kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

tDHSB

RWI

Figure 15. Soft Sequence Processing[29, 30]

	Soft Sequence		tSS	Soft Sequence		tSS
	Command			Command
Address	Address #1	Address #6		Address #1	Address #6
	tSA		tCW		tCW
CE
VCC

Notes

29.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

30.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-42879 Rev. *B

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Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationNot to scale PinoutsTop View Byte Low Enable, Active LOW. Controls DQ7 DQ0 Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 DQ8 Power Supply Inputs to the Device .0V +20%, -10%Sram Write Device OperationSram Read AutoStore OperationA15 A09 Mode Power Hardware Recall Power UpMode Selection Software StoreData Protection Mode Selection A15 A09Preventing AutoStore Noise ConsiderationsOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min MaxDescription 20ns 25ns 45ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthInputs/Outputs Mode Power Truth Table for x8 Configuration Inputs/Outputs Mode PowerTruth Table for x16 Configuration Truth Table For Sram OperationsOrdering Information CY14B101LA-BA25XCT CY14B101LA-ZS25XCTCY14B101LA-ZS25XC CY14B101LA-BA25XCCY14B101LA-BA45XCT CY14B101LA-ZS45XCTCY14B101LA-ZS45XC CY14B101LA-BA45XCZS Tsop Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic GVCH/AESA Document HistoryUNC/PYRS GVCH/PYRSSales, Solutions, and Legal Information USB