Cypress CY14B101NA, CY14B101LA manual Sram Write Cycle #2 CE Controlled 3, 18, 19

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PRELIMINARY CY14B101LA, CY14B101NA

Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21]

Address

BHE, BLE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 18, 19, 21]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-42879 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionNot to scale PinoutsTop View Power Supply Inputs to the Device .0V +20%, -10% Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 DQ8 Byte Low Enable, Active LOW. Controls DQ7 DQ0AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A09 Mode PowerNoise Considerations Mode Selection A15 A09Preventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallDescription 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20ns 25ns 45ns Unit Min MaxTruth Table For Sram Operations Truth Table for x8 Configuration Inputs/Outputs Mode PowerTruth Table for x16 Configuration Inputs/Outputs Mode PowerOrdering Information CY14B101LA-BA25XC CY14B101LA-ZS25XCTCY14B101LA-ZS25XC CY14B101LA-BA25XCTCY14B101LA-BA45XC CY14B101LA-ZS45XCTCY14B101LA-ZS45XC CY14B101LA-BA45XCTNvsram Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic GVCH/PYRS Document HistoryUNC/PYRS GVCH/AESAUSB Sales, Solutions, and Legal Information

Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21]

BHE, BLE

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 18, 19, 21]

BHE, BLE