Cypress CY14B101NA, CY14B101LA manual Software Controlled STORE/RECALL Cycle

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PRELIMINARY

CY14B101LA, CY14B101NA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software Controlled STORE/RECALL Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameters[27, 28]

 

 

Description

20 ns

25 ns

45 ns

Unit

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

tRC

STORE/RECALL Initiation Cycle Time

20

 

25

 

45

 

ns

tSA

Address Setup Time

0

 

0

 

0

 

ns

tCW

Clock Pulse Width

15

 

20

 

30

 

ns

tHA

Address Hold Time

0

 

0

 

0

 

ns

tRECALL

RECALL Duration

 

200

 

200

 

200

µs

Switching Waveforms

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[28]

 

 

tRC

tRC

 

Address

 

Address #1

Address #6

 

 

tSA

tCW

tCW

 

 

 

 

CE

 

tHA

tHA

 

t

 

 

SA

tHA

 

 

t

 

 

 

 

 

 

 

HA

 

OE

 

 

 

 

 

 

 

tDELAY

tHHHD

HSB (STORE only)

tLZCE

tHZCE

 

tLZHSB

 

 

High Impedance

DQ (DATA)

 

 

 

 

 

tSTORE/tRECALL

 

 

 

 

 

RWI

 

 

 

 

 

 

Figure 13. Autostore Enable / Disable Cycle

 

 

tRC

Address

Address #1

tSA

tCW

CE

 

tSA

 

OE

 

tLZCE

 

DQ (DATA)

 

 

tRC

 

Address #6

 

tCW

tHA

tHA

tHA

t

 

HA

tHZCE

tSS

tDELAY

 

Notes

27.The software sequence is clocked with CE controlled or OE controlled reads.

28.The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE must be HIGH during all six consecutive cycles.

Document #: 001-42879 Rev. *B

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale Byte High Enable, Active LOW. Controls DQ15 DQ8 Output Enable, Active LOW. The active LOWByte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10%Sram Read Device OperationSram Write AutoStore OperationMode Selection Hardware Recall Power UpA15 A09 Mode Power Software StorePreventing AutoStore Mode Selection A15 A09Data Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallDescription 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store Cycle To Output Active Time when write latch not setDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse WidthTruth Table for x16 Configuration Truth Table for x8 Configuration Inputs/Outputs Mode PowerInputs/Outputs Mode Power Truth Table For Sram OperationsOrdering Information CY14B101LA-ZS25XC CY14B101LA-ZS25XCTCY14B101LA-BA25XCT CY14B101LA-BA25XCCY14B101LA-ZS45XC CY14B101LA-ZS45XCTCY14B101LA-BA45XCT CY14B101LA-BA45XCCY 14 B 101L A-ZS 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic UNC/PYRS Document HistoryGVCH/AESA GVCH/PYRSUSB Sales, Solutions, and Legal Information