Cypress CY14B101LA, CY14B101NA manual Package Diagrams, Pin Tsop II

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PRELIMINARY CY14B101LA, CY14B101NA

Package Diagrams

Figure 16. 44-Pin TSOP II (51-85087)

22	1	PIN 1 I.D.
22	1
	11.938 (0.470)	11.735 (0.462)	10.262 (0.404)	10.058 (0.396)
23	44

DIMENSION IN MM (INCH)

MAX

MIN.

O R E

K X A

S G

EJECTOR PIN

TOP VIEW

BOTTOM VIEW

0.800 BSC	0.400(0.016)
	0.300 (0.012)	BASE PLANE
(0.0315)

0° -5°

0.10 (.004)

18.517 (0.729)

18.313 (0.721)

(0.047)1.194	(0.039)0.991	(0.0059)0.150	(0.0020)0.050	SEATING

				PLANE

10.262 (0.404)

10.058 (0.396)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

51-85087-*A

Document #: 001-42879 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationNot to scale PinoutsTop View Output Enable, Active LOW. The active LOW Byte High Enable, Active LOW. Controls DQ15 DQ8Byte Low Enable, Active LOW. Controls DQ7 DQ0 Power Supply Inputs to the Device .0V +20%, -10%Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A09 Mode Power Software StoreMode Selection A15 A09 Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min MaxTo Output Active Time when write latch not set Hardware Store CycleDescription 20ns 25ns 45ns Unit Min Max Hardware Store Pulse WidthTruth Table for x8 Configuration Inputs/Outputs Mode Power Truth Table for x16 ConfigurationInputs/Outputs Mode Power Truth Table For Sram OperationsOrdering Information CY14B101LA-ZS25XCT CY14B101LA-ZS25XCCY14B101LA-BA25XCT CY14B101LA-BA25XCCY14B101LA-ZS45XCT CY14B101LA-ZS45XCCY14B101LA-BA45XCT CY14B101LA-BA45XCPart Numbering Nomenclature CY 14 B 101L A-ZS 20 X C TZS Tsop NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic Document History UNC/PYRSGVCH/AESA GVCH/PYRSSales, Solutions, and Legal Information USB