Cypress manual CY14B101LA-ZS45XCT, CY14B101LA-BA45XCT, CY14B101LA-SP45XCT, CY14B101LA-SZ45XCT

Page 18

 

 

 

 

PRELIMINARY

CY14B101LA, CY14B101NA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ordering Information (continued)

 

 

 

 

 

 

 

 

 

 

 

 

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Diagram

Range

 

 

 

 

 

45

CY14B101LA-ZS45XCT

51-85087

44-pin TSOP II

 

Commercial

 

 

 

 

 

 

 

CY14B101LA-ZS45XC

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101LA-BA45XCT

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101LA-BA45XC

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101LA-SP45XCT

51-85061

48-pin SSOP

 

 

 

 

 

 

 

 

 

CY14B101LA-SP45XC

51-85061

48-pin SSOP

 

 

 

 

 

 

 

 

 

CY14B101LA-SZ45XCT

51-85127

32-pin SOIC

 

 

 

 

 

 

 

 

 

CY14B101LA-SZ45XC

51-85127

32-pin SOIC

 

 

 

 

 

 

 

 

 

CY14B101NA-ZS45XCT

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101NA-ZS45XC

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101NA-BA45XCT

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101NA-BA45XC

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101LA-ZS45XIT

51-85087

44-pin TSOP II

 

Industrial

 

 

 

 

 

 

 

CY14B101LA-ZS45XI

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101LA-BA45XIT

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101LA-BA45XI

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101LA-SP45XIT

51-85061

48-pin SSOP

 

 

 

 

 

 

 

 

 

CY14B101LA-SP45XI

51-85061

48-pin SSOP

 

 

 

 

 

 

 

 

 

CY14B101LA-SZ45XIT

51-85127

32-pin SOIC

 

 

 

 

 

 

 

 

 

CY14B101LA-SZ45XI

51-85127

32-pin SOIC

 

 

 

 

 

 

 

 

 

CY14B101NA-ZS45XIT

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101NA-ZS45XI

51-85087

44-pin TSOP II

 

 

 

 

 

 

 

 

 

CY14B101NA-BA45XIT

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

CY14B101NA-BA45XI

51-85128

48-ball FBGA

 

 

 

 

 

 

 

 

 

 

All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.

Document #: 001-42879 Rev. *B

Page 18 of 25

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Image 18
Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationPinouts Top ViewNot to scale Byte Low Enable, Active LOW. Controls DQ7 DQ0 Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 DQ8 Power Supply Inputs to the Device .0V +20%, -10%Sram Write Device OperationSram Read AutoStore OperationA15 A09 Mode Power Hardware Recall Power UpMode Selection Software StoreData Protection Mode Selection A15 A09Preventing AutoStore Noise ConsiderationsOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleSram Read Cycle #2 CE and OE Controlled 3, 15 Sram Write Cycle #2 CE Controlled 3, 18, 19 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min MaxDescription 20ns 25ns 45ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthInputs/Outputs Mode Power Truth Table for x8 Configuration Inputs/Outputs Mode PowerTruth Table for x16 Configuration Truth Table For Sram OperationsOrdering Information CY14B101LA-BA25XCT CY14B101LA-ZS25XCTCY14B101LA-ZS25XC CY14B101LA-BA25XCCY14B101LA-BA45XCT CY14B101LA-ZS45XCTCY14B101LA-ZS45XC CY14B101LA-BA45XCZS Tsop Part Numbering NomenclatureCY 14 B 101L A-ZS 20 X C T NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm Pin Ssop Pin Soic GVCH/AESA Document HistoryUNC/PYRS GVCH/PYRSSales, Solutions, and Legal Information USB