Contents
Logic Block Diagram1, 2
Features
Functional Description
Cypress Semiconductor Corporation
Not to scale
Pinouts
Top View
Byte High Enable, Active LOW. Controls DQ15 DQ8
Output Enable, Active LOW. The active LOW
Byte Low Enable, Active LOW. Controls DQ7 DQ0
Power Supply Inputs to the Device .0V +20%, -10%
Sram Read
Device Operation
Sram Write
AutoStore Operation
Mode Selection
Hardware Recall Power Up
A15 A09 Mode Power
Software Store
Preventing AutoStore
Mode Selection A15 A09
Data Protection
Noise Considerations
Maximum Ratings
DC Electrical Characteristics
Operating Range
Range
Capacitance
Data Retention and Endurance
Thermal Resistance
AC Test Conditions
Switching Waveforms
AC Switching Characteristics
Parameters Sram Read Cycle
Sram Write Cycle
Sram Read Cycle #2 CE and OE Controlled 3, 15
Sram Write Cycle #2 CE Controlled 3, 18, 19
Parameters Description 20 ns 25 ns 45 ns Unit Min Max
AutoStore/Power Up Recall
Description 20 ns 25 ns 45 ns Unit Min Max
Software Controlled STORE/RECALL Cycle
Hardware Store Cycle
To Output Active Time when write latch not set
Description 20ns 25ns 45ns Unit Min Max
Hardware Store Pulse Width
Truth Table for x16 Configuration
Truth Table for x8 Configuration Inputs/Outputs Mode Power
Inputs/Outputs Mode Power
Truth Table For Sram Operations
Ordering Information
CY14B101LA-ZS25XC
CY14B101LA-ZS25XCT
CY14B101LA-BA25XCT
CY14B101LA-BA25XC
CY14B101LA-ZS45XC
CY14B101LA-ZS45XCT
CY14B101LA-BA45XCT
CY14B101LA-BA45XC
CY 14 B 101L A-ZS 20 X C T
Part Numbering Nomenclature
ZS Tsop
Nvsram
Pin Tsop II
Package Diagrams
Ball Fbga 6 mm x 10 mm x 1.2 mm
Pin Ssop
Pin Soic
UNC/PYRS
Document History
GVCH/AESA
GVCH/PYRS
USB
Sales, Solutions, and Legal Information
