GE863-QUAD
1vv0300715 Rev. 1 - 19/09/06
6.2MODEM SERIAL PORT 2 (Python Debug)
It is available on the following pins:
PIN # | NAME | DESCRIPTION | TYPE |
25 | TX_TRACE | TX Data | CMOS 2.8V |
26 | RX_TRACE | RX Data | CMOS 2.8V |
6.3RS232 level translation
In order to interface the Telit
•invert the electrical signal in both directions
•change the level from 0/3V to
Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with lower levels on the RS232 side
The simplest way to translate the levels and invert the signal is by using a single chip level translator. There are a multitude of them, differing in the number of driver and receiver and in the levels (be sure to get a true RS232 level translator not a RS485 or other standards).
By convention the driver is the level translator from the
In order to translate the whole set of control lines of the UART you will need:
•5 driver
•3 receiver
NOTE: The digital input lines working at 2.8VCMOS have an absolute maximum input voltage of 3,75V; therefore the level translator IC shall not be powered by the +3.8V supply of the module. Instead it shall be powered from a +2.8V / +3.0V (dedicated) power supply.
This is because in this way the level translator IC outputs on the module side (i.e. GE863- QUAD/PY inputs) will work at +3.8V interface levels, stressing the module inputs at its maximum input voltage.
This can be acceptable for evaluation purposes, but not on production devices.
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