SDI Technologies SDIO Card manual Sdio Interrupts, Interrupt Timing

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©Copyright 2000-2007 SD Card Association

SDIO Simplified Specification Version 2.00

8.SDIO Interrupts

In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the SD interface. Pin number 8, which is used as DAT[1] when operating in the 4-bit SD mode, is used to signal the card’s interrupt to the host. The use of interrupt is optional for each card or function within a card. The SDIO interrupt is “level sensitive”, that is, the interrupt line shall be held active (low) until it is either recognized and acted upon by the host or de-asserted due to the end of the Interrupt Period (see 8.1.2). Once the host has serviced the interrupt, it is cleared via some function unique I/O operation. All hosts shall provide pull-up resistors on all data lines DAT[3:0] as described in section 6 of the SD Physical Specification.

8.1Interrupt Timing

The operation of the interrupt pin is different between the SPI mode and the SD mode. The operation of the interrupt pin is defined as follows:

8.1.1SPI and SD 1-bit Mode Interrupts

In the SPI and 1-bit SD mode, Pin 8 is dedicated to the interrupt function. Thus, in the SPI and SD 1-bit modes there are no timing constraints on interrupts. A card in the SPI or 1-bit SD mode signals an interrupt to the host at any time by asserting pin 8 low. The host detects this pending interrupt using a level sensitive input. The host is responsible for clearing the interrupt. If the SDIO card is operating in the SPI mode, the interrupt from the card may not be asserted if the card is not selected.(CS=0). The exception to this requirement occurs only if the card is both capable of interrupting when not selected (the SCSI bit in the CCCR = 1), and has that feature turned on (the ECSI bit = 1). In this case, the card may assert the interrupt irrespective of the state of the CS line. For more information, see Table 6-1.

8.1.2SD 4-bit Mode

Since Pin 8 is shared between the IRQ and DAT[1] use in the 4-bit SD mode, an interrupt shall only be sent by the card and recognized by the host during a specific time. The time that a low on Pin 8 shall be recognized as an interrupt is defined as the Interrupt Period.

An SDIO host shall only sample the level on Pin 8 (DAT[1]/IRQ) into the interrupt detector during the Interrupt Period. At all other times, the host interrupt controller shall ignore the level on Pin 8. Note that the Interrupt Period is applicable for both memory and I/O operations

The definition of the Interrupt Period is different for operations with single block and multiple block data transfer.

8.1.3Interrupt Period Definition

This section is not included in the Simplified Specification.

8.1.4Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional) This section is not included in the Simplified Specification.

8.1.5Inhibited Interrupts (Removed Section)

This section is not included in the Simplified Specification.

8.1.6End of Interrupt Cycles

This section is not included in the Simplified Specification.

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Contents SD Specifications Part E1 Sdio Simplified Specification Changes compared to previous issue Sdio Simplified Specification VersionDate Version Release of SD Simplified Specification Conventions Used in This Document Table of Contents SPI and SD 1-bit Mode Interrupts 16.2 Table of Tables Table of Figures General Description Sdio FeaturesPrimary Reference Document Standard Sdio FunctionsSdio Card Types Sdio Signaling DefinitionSdio Card modes Sdio Host ModesSignal connection to two 4-bit Sdio cards Signal PinsSdio Card Initialization ResetDifferences in I/O card Initialization Sdio Simplified Specification Version MEM=0 Card initialization flow in SD mode Sdio aware host Illegal Command F8=0 Card initialization flow in SPI mode Sdio aware host VDD Voltage Window Position Iosendopcond Command CMD5OCR Values for CMD5 OCR bitIosendopcond Response R4 Response R4 in SD modeRecommendations for RCA after Reset Acceptable Commands after InitializationSpecial Initialization considerations for Combo Cards Re-initialize both I/O and MemoryRe-Initialization Flow for Memory controller Re-Initialization Flow for I/O ControllerEnabling CRC in SPI Combo Card Sdio Command List Differences with SD Memory SpecificationUnsupported SD Memory Commands Modified R6 Response Reset for SdioBus Width Timings Card Detect ResistorCombo Card 4-bit Control Card Detect Resistor StatesData Transfer Abort Data Transfer Block SizesChanges to SD Memory Fixed Registers Read AbortCID Register OCR RegisterCSD Register RCA RegisterClear Sdio Status Register StructureBit Identifier Type Value Description Iorwdirect Command CMD52 New I/O Read/Write CommandsIllegalcommand ComcrcerrorIorwdirect Response R5 1 CMD52 Response SD modesIdentifier Type Value Description Clear Condition DIS=DisabledCMD=DAT lines free TRN=TransferIorw Extended command Op Code Definition Iorwextended Command CMD53OP code Command operation CRC1 CMD53 Data Transfer Format Byte Count ValuesSdio Card Internal Operation Register Access TimeOverview InterruptsRead Wait Suspend/ResumeCMD52 During Data Transfer Sdio Fixed Internal MapCard Common Control Registers Cccr Common I/O Area CIAType Card Common Control Registers CccrCCCR/SDIO IOE3To abort transfers to/from memory Scsi 4BLS Transaction of function 0 CIA Empc Cccr bit DefinitionsAddress Function Basic Registers FBRFunction Basic Information Registers FBR Field TypeFBR bit and field definitions Sdio Simplified Specification Version Field TypeCard Information Structure CIS Setting Block Size with CMD53Multiple Function Sdio Cards Card Information Structure CIS and reserved area of CIAState Diagram for Bus State Machine Bus State DiagramEmbedded I/O Code Storage Area CSA CSA AccessCSA Data Format Interrupt Timing Sdio InterruptsInterrupt Clear Timing Terminated Data Transfer Interrupt CycleSdio Suspend/Resume Operation Sdio Read Wait Operation Power Control Overview Power ControlPower Control support for Sdio Cards Master Power ControlPower Selection Power Control Support for the Sdio HostHigh-Power Tuples Reference Tuples by Master Power Control and Power SelectPower Control Operation Sdio High-Speed Mode High-Speed ModeSwitching Bus Speed Mode in a Combo Card Sdio Physical Properties Sdio PowerSdio Simplified Specification Version Inrush Current Limiting CIS Reference Document CIS FormatsBasic Tuple Format and Tuple Chain Structure Byte Order Within TuplesSdio Card Metaformat Tuple VersionTuples Supported by Sdio Cards Code Name DescriptionSdio Specific Extensions Cistplmanfid Manufacturer Identification String TupleCistplmanfid Manufacturer Identification Tuple Cistplfuncid Function Identification TupleCistplfunce Tuple General Structure Cistplfunce Function Extension TupleCistplfunce Tuple for Function 0 common Tplfidfunction Tuple for Function 0 commonTplfidfunction Tuple for Function Cistplfunce Tuple for FunctionByte Sdio Simplified Specification Version 10 Tplfefunctioninfo Definition Tplfidfunction Field Descriptions for Functions11 Tplfecsaproperty Definition Bit Name12 Cistplsdiostd Tuple Reserved for Sdio Cards Cistplsdiostd Function is a Standard Sdio FunctionCistplsdioext Tuple Reserved for Sdio Cards 13 Cistplsdioext Tuple Reserved for Sdio CardsTable A-14 SD Mode Command List SD and SPI Command ListNormative Sdmem Sdio Table A-15 SPI Mode Command ListNormative References Appendix BAbbreviations and Terms Appendix CLOW, High Informative
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