SDI Technologies SDIO Card manual Terminated Data Transfer Interrupt Cycle, Interrupt Clear Timing

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©Copyright 2000-2007 SD Card Association

SDIO Simplified Specification Version 2.00

8.1.7Terminated Data Transfer Interrupt Cycle

This section is not included in the Simplified Specification.

8.1.8Interrupt Clear Timing

Since the SDIO card uses level sensitive interrupts, the host shall clear pending interrupts with an I/O read or write to some function unique area. In some host implementations, the sending of a CMD52 to the card is handled by host adapter hardware while the host CPU can execute other operations. This condition may allow an interrupt that has already been handled to re-interrupt the host if the timing of the interrupt clear is not controlled. To prevent this condition, Any SDIO card that implements interrupts shall follow some required timing with respect to removing the interrupt from the DAT[1] line after the write to the function unique area that clears the interrupt. The clearing of the interrupt can be caused by an I/O write in a function unique method, or by a function unique I/O read. An example of clearing an interrupt using an I/O read would be a function where the reading of a data register may automatically clear the data ready interrupt.

The rest of this section is not included in the Simplified Specification.

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Contents SD Specifications Part E1 Sdio Simplified Specification Date Version Sdio Simplified Specification VersionChanges compared to previous issue Release of SD Simplified Specification Conventions Used in This Document Table of Contents SPI and SD 1-bit Mode Interrupts 16.2 Table of Tables Table of Figures Primary Reference Document Sdio FeaturesGeneral Description Standard Sdio FunctionsSdio Card modes Sdio Signaling DefinitionSdio Card Types Sdio Host ModesSignal Pins Signal connection to two 4-bit Sdio cardsDifferences in I/O card Initialization ResetSdio Card Initialization Sdio Simplified Specification Version MEM=0 Card initialization flow in SD mode Sdio aware host Illegal Command F8=0 Card initialization flow in SPI mode Sdio aware host OCR Values for CMD5 Iosendopcond Command CMD5VDD Voltage Window Position OCR bitResponse R4 in SD mode Iosendopcond Response R4Special Initialization considerations for Combo Cards Acceptable Commands after InitializationRecommendations for RCA after Reset Re-initialize both I/O and MemoryRe-Initialization Flow for I/O Controller Re-Initialization Flow for Memory controllerEnabling CRC in SPI Combo Card Unsupported SD Memory Commands Differences with SD Memory SpecificationSdio Command List Bus Width Reset for SdioModified R6 Response Combo Card 4-bit Control Card Detect ResistorTimings Card Detect Resistor StatesChanges to SD Memory Fixed Registers Data Transfer Block SizesData Transfer Abort Read AbortCSD Register OCR RegisterCID Register RCA RegisterBit Identifier Type Value Description Sdio Status Register StructureClear New I/O Read/Write Commands Iorwdirect Command CMD52Iorwdirect Response R5 ComcrcerrorIllegalcommand 1 CMD52 Response SD modesCMD=DAT lines free DIS=DisabledIdentifier Type Value Description Clear Condition TRN=TransferOP code Command operation Iorwextended Command CMD53Iorw Extended command Op Code Definition CRCByte Count Values 1 CMD53 Data Transfer FormatOverview Register Access TimeSdio Card Internal Operation InterruptsCMD52 During Data Transfer Suspend/ResumeRead Wait Sdio Fixed Internal MapCommon I/O Area CIA Card Common Control Registers CccrCCCR/SDIO Card Common Control Registers CccrType IOE3To abort transfers to/from memory Scsi 4BLS Transaction of function 0 CIA Cccr bit Definitions EmpcFunction Basic Information Registers FBR Function Basic Registers FBRAddress Field TypeSdio Simplified Specification Version Field Type FBR bit and field definitionsMultiple Function Sdio Cards Setting Block Size with CMD53Card Information Structure CIS Card Information Structure CIS and reserved area of CIABus State Diagram State Diagram for Bus State MachineCSA Data Format CSA AccessEmbedded I/O Code Storage Area CSA Sdio Interrupts Interrupt TimingTerminated Data Transfer Interrupt Cycle Interrupt Clear TimingSdio Suspend/Resume Operation Sdio Read Wait Operation Power Control support for Sdio Cards Power ControlPower Control Overview Master Power ControlHigh-Power Tuples Power Control Support for the Sdio HostPower Selection Reference Tuples by Master Power Control and Power SelectPower Control Operation Switching Bus Speed Mode in a Combo Card High-Speed ModeSdio High-Speed Mode Sdio Power Sdio Physical PropertiesSdio Simplified Specification Version Inrush Current Limiting Basic Tuple Format and Tuple Chain Structure CIS FormatsCIS Reference Document Byte Order Within TuplesTuples Supported by Sdio Cards Tuple VersionSdio Card Metaformat Code Name DescriptionCistplmanfid Manufacturer Identification Tuple Cistplmanfid Manufacturer Identification String TupleSdio Specific Extensions Cistplfuncid Function Identification TupleCistplfunce Tuple for Function 0 common Cistplfunce Function Extension TupleCistplfunce Tuple General Structure Tplfidfunction Tuple for Function 0 commonByte Cistplfunce Tuple for FunctionTplfidfunction Tuple for Function Sdio Simplified Specification Version 11 Tplfecsaproperty Definition Tplfidfunction Field Descriptions for Functions10 Tplfefunctioninfo Definition Bit NameCistplsdioext Tuple Reserved for Sdio Cards Cistplsdiostd Function is a Standard Sdio Function12 Cistplsdiostd Tuple Reserved for Sdio Cards 13 Cistplsdioext Tuple Reserved for Sdio CardsNormative SD and SPI Command ListTable A-14 SD Mode Command List Table A-15 SPI Mode Command List Sdmem SdioAppendix B Normative ReferencesAppendix C Abbreviations and TermsLOW, High Informative