SDI Technologies SDIO Card Sdio High-Speed Mode, Switching Bus Speed Mode in a Combo Card

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©Copyright 2000-2007 SD Card Association

SDIO Simplified Specification Version 2.00

12. High-Speed Mode

High-Speed mode increases the bus clock rate to 50MHz and the SD bus throughput from 12.5MB/sec to 25MB/sec. For information on High-Speed mode for SD memory cards see Part 1 Physical Layer Specification Version 2.00, sections 4.3.10, 4.3.11 and 6.8. SDIO and combo cards may also support High-Speed mode.

12.1SDIO High-Speed Mode

SDIO version 1.20 cards indicate their support for High-Speed mode with the SHS (Support High-Speed) bit in the CCCR (See section 6.9). Hosts switch between default and High-Speed mode with the EHS (Enable High-Speed) bit in the CCCR by CMD52. Following a command to set or clear EHS, cards shall switch speed mode within 8 clocks after the end bit of the corresponding response.

When switching from default to High-Speed mode the host can try to set EHS without first checking SHS. The host issues CMD52 in RAW mode, setting EHS to one, and after getting the response of CMD52 the host checks SHS and EHS. If SHS=0 or EHS=0, the command will be ignored and the card is still in default mode. If SHS=1 and EHS=1, the card is in High-Speed Mode.

12.2Switching Bus Speed Mode in a Combo Card

A combo card that supports High-Speed shall support it for both memory and IO. Two bus speed switch commands are defined; SD memory command (CMD6) and SDIO command (EHS in CCCR is changed using CMD52).

A part of this section is not included in the Simplified Specification.

When one bus speed switch commands is executed successfully, the card switches the card bus speed mode. If two bus speed switch commands are executed in turn (to the same bus speed mode), only the first successful command is effective to switch bus speed mode.

The host needs to check success of executing bus speed switch command and then the host can switch the host bus speed mode to the same one.

Success of switching bus speed mode is determined by checking receipt of a good response and the result of switching bus speed mode is the same as the switch requested.

The status of current bus speed mode is read by bus speed switch commands. For example, when bus speed mode is switched by CMD6, the result can be read from EHS. If switching by RAW mode of CMD52 has failed, there are two kinds of responses. One is no response with illegal command error. The other is that CMD52 is accepted and the status of RAW mode indicates EHS is not changed.

A reset of either the memory or IO portion of a combo card will also reset both portions to default speed mode. Within 8 clocks after response of a reset by CMD52 (write to RES in CCCR) or CMD0 the card shall change the speed mode to default speed mode.

Note that when changing the bus speed the host bus driver should treat a bus speed change request from any driver as an atomic operation. The host should mask interrupts and not issue any command to the card until the bus speed change is complete.

If a combo card supports the Lock/unlock function, a locked card cannot change bus speed mode. A locked card indicates an illegal command error to a bus speed switch command. The host needs to unlock the card by CMD42 before changing bus speed. It also implies that a host should not change bus speed mode during initialization before managing a locked card.

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Contents SD Specifications Part E1 Sdio Simplified Specification Date Version Sdio Simplified Specification VersionChanges compared to previous issue Release of SD Simplified Specification Conventions Used in This Document Table of Contents SPI and SD 1-bit Mode Interrupts 16.2 Table of Tables Table of Figures Sdio Features General DescriptionPrimary Reference Document Standard Sdio FunctionsSdio Signaling Definition Sdio Card TypesSdio Card modes Sdio Host ModesSignal Pins Signal connection to two 4-bit Sdio cardsDifferences in I/O card Initialization ResetSdio Card Initialization Sdio Simplified Specification Version MEM=0 Card initialization flow in SD mode Sdio aware host Illegal Command F8=0 Card initialization flow in SPI mode Sdio aware host Iosendopcond Command CMD5 VDD Voltage Window PositionOCR Values for CMD5 OCR bitResponse R4 in SD mode Iosendopcond Response R4Acceptable Commands after Initialization Recommendations for RCA after ResetSpecial Initialization considerations for Combo Cards Re-initialize both I/O and MemoryRe-Initialization Flow for I/O Controller Re-Initialization Flow for Memory controllerEnabling CRC in SPI Combo Card Unsupported SD Memory Commands Differences with SD Memory SpecificationSdio Command List Bus Width Reset for SdioModified R6 Response Card Detect Resistor TimingsCombo Card 4-bit Control Card Detect Resistor StatesData Transfer Block Sizes Data Transfer AbortChanges to SD Memory Fixed Registers Read AbortOCR Register CID RegisterCSD Register RCA RegisterBit Identifier Type Value Description Sdio Status Register StructureClear New I/O Read/Write Commands Iorwdirect Command CMD52Comcrcerror IllegalcommandIorwdirect Response R5 1 CMD52 Response SD modesDIS=Disabled Identifier Type Value Description Clear ConditionCMD=DAT lines free TRN=TransferIorwextended Command CMD53 Iorw Extended command Op Code DefinitionOP code Command operation CRCByte Count Values 1 CMD53 Data Transfer FormatRegister Access Time Sdio Card Internal OperationOverview InterruptsSuspend/Resume Read WaitCMD52 During Data Transfer Sdio Fixed Internal MapCommon I/O Area CIA Card Common Control Registers CccrCard Common Control Registers Cccr TypeCCCR/SDIO IOE3To abort transfers to/from memory Scsi 4BLS Transaction of function 0 CIA Cccr bit Definitions EmpcFunction Basic Registers FBR AddressFunction Basic Information Registers FBR Field TypeSdio Simplified Specification Version Field Type FBR bit and field definitionsSetting Block Size with CMD53 Card Information Structure CISMultiple Function Sdio Cards Card Information Structure CIS and reserved area of CIABus State Diagram State Diagram for Bus State MachineCSA Data Format CSA AccessEmbedded I/O Code Storage Area CSA Sdio Interrupts Interrupt TimingTerminated Data Transfer Interrupt Cycle Interrupt Clear TimingSdio Suspend/Resume Operation Sdio Read Wait Operation Power Control Power Control OverviewPower Control support for Sdio Cards Master Power ControlPower Control Support for the Sdio Host Power SelectionHigh-Power Tuples Reference Tuples by Master Power Control and Power SelectPower Control Operation Switching Bus Speed Mode in a Combo Card High-Speed ModeSdio High-Speed Mode Sdio Power Sdio Physical PropertiesSdio Simplified Specification Version Inrush Current Limiting CIS Formats CIS Reference DocumentBasic Tuple Format and Tuple Chain Structure Byte Order Within TuplesTuple Version Sdio Card MetaformatTuples Supported by Sdio Cards Code Name DescriptionCistplmanfid Manufacturer Identification String Tuple Sdio Specific ExtensionsCistplmanfid Manufacturer Identification Tuple Cistplfuncid Function Identification TupleCistplfunce Function Extension Tuple Cistplfunce Tuple General StructureCistplfunce Tuple for Function 0 common Tplfidfunction Tuple for Function 0 commonByte Cistplfunce Tuple for FunctionTplfidfunction Tuple for Function Sdio Simplified Specification Version Tplfidfunction Field Descriptions for Functions 10 Tplfefunctioninfo Definition11 Tplfecsaproperty Definition Bit NameCistplsdiostd Function is a Standard Sdio Function 12 Cistplsdiostd Tuple Reserved for Sdio CardsCistplsdioext Tuple Reserved for Sdio Cards 13 Cistplsdioext Tuple Reserved for Sdio CardsNormative SD and SPI Command ListTable A-14 SD Mode Command List Table A-15 SPI Mode Command List Sdmem SdioAppendix B Normative ReferencesAppendix C Abbreviations and TermsLOW, High Informative
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