Toshiba TW40F80 manual Sub Screen Process Section, Sub screen process section

Page 48

4-2. Sub Screen Process Section

The sub screen process section is shown in Fig. 6-3.

The Y, I and Q signals from the video/color/deflection pro- cess section are limited in their frequency bandwidth by the LPF in the prceeding stage and input to pins 6, 13 and 15 of QY03.

The frequency of 18.5 MHz generated by LY102 is multi- plied by 1/2 inside QY03. The Y signal is sampled by 9.25 MHz and the I and Q signals are sampled by 4.63 MHz (1/2 frequency to multiplex) and then the signals are converted into 8-bit digital signals.

The horizontal sync signal WHD (the signal mixed with WHD1 and WHD2 by QY43) for writing input to pins 21 and 20 of QY03 and the vertical sync signal WVD for trig- ger writing on the field memory QY10 and QY11.

The horizontal sync signal RHD for reading-out and the ver- tical sync signal RVD for reading out input to pins 75 and 77 of QY03 trigger the reading at 18.0 MHz which is created by 2/3-multiplying 27.0 MHz developed in LY101and then output as the analog signal.

The Y, I and Q signals converted for the sub screen are out- put from pins 95, 100 and 97 of QY03. The output signals are used for the input signals compressed by 1/2 in the hori- zontal direction in the double window mode and for the in- put signal compressed by 1/6 in the horizontal direction and by 1/3 in the vertical direction in 9-screen multi-search mode.

Then the signals are smoothed by the LPF in the next stage then input to the main/sub screen superimposing section.

Video/color/deflection process section

Signal reception circuit

 

 

 

 

QY03 TC9092AF

 

 

 

 

 

 

Sub screen process IC

 

 

 

Y

L.P.F

6

Y IN

Y OUT

95

L.P.F

Y

 

 

I

L.P.F

13

R-Y IN

R-Y OUT(I)

100

L.P.F

I

 

 

Q

L.P.F

15

B-Y IN

B-Y OUT(Q)

97

L.P.F

Q

 

 

I2C BUS (SCL, SDA)

 

 

79

SCL

YS OUT

70

YS

 

 

 

 

 

 

 

 

 

 

 

 

 

80

SDA

 

 

QY10, QY11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSM518221-30ZS

WVD

 

 

 

 

20

FVS

MWD 0

48

2M

 

 

 

 

 

 

memory

 

 

 

 

 

 

 

 

 

 

WHD2

1

OR

 

WHD

 

 

 

 

Date in

 

 

 

 

 

 

 

 

4

21

FHS

 

32

 

WHD1

2

circuit

 

MWD15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QY43

 

 

24

OSCSI

 

 

 

 

 

TC7S32F

 

 

25

OSCSO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LY102

 

 

MRD 0

51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

77

FVM

 

 

Date out

 

 

 

 

 

 

 

 

MRD15

65

 

PY01

 

 

 

 

75

FHM

 

 

 

 

 

 

 

 

 

 

 

 

 

RVD

 

 

 

 

72

OSCMI

 

 

 

Y11

 

 

 

 

73

OSCMO

 

 

 

 

 

 

 

 

 

 

 

 

RHD

 

 

 

LY101

 

 

 

 

 

Y12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y01

YS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

To Main/Sub pictore superimposing process section

Fig. 6-3 Sub screen process section

48

Page 47 Page 49
Image 48
Page 47 Page 49
Contents TW40F80 Contents Terminal FUNCTION, Description and Block Diagram Wide Aspect Conversion Circuit Failure AnalysisSection X Deflection Distortion Correction Circuit Section XI Digital Convergence CircuitSection Feature Improved ServiceabilityOutline Merits of BUS System Reduction of Parts CountSpecifications Chassis ModelFront View Video 3 InputsRear View IN-VIDEORemote Control View 100Chassis Layout Starsight Newosd FRO. SurrConstruction of Chassis Major Features Section II TUNER, IF/MTS/S. PRO Module Circuit BlockOutline RF AGCAudio Multiplex Demodulation Circuit A.PRO block diagram A.PRO Section Audio ProcessorConfiguration of the audio circuit and signal flow are given POP Tuner Terminal No NameOperation of Channel Selection Circuit Microcomputer SDA SCLMicrocomputer Terminal Function Microcomputer Terminal Name and Operation Logic Terminal Name Function In/Out Logic RemarksOn Screen Function EEPROMQA02SDA System Block Diagram Local KEY Detection Method Local key assignment FunctionRemote Control Code Assignment Code FunctionTo TV set Custom codes are 40-BFH TV set for North U.S.A Code Function Optional Setting for Each Model OPT0 OPT1 Models HEXEntering to Service Mode Test Signal SelectionService Adjustment Failure Diagnosis Procedure Contents to be Confirmed by CustomerExecuting Self Diagnosis Function Understanding Self Diagnosis Indication Self CheckClearing method of self diagnosis result Troubleshooting Chart TV does Not Turned onYES No Acception of KEY-IN No Picture Snow NoiseMemory Circuit Check No Indication On ScreenSection IV DVD Switch Circuit DVD Switch Block Diagram Outline Configuration Section V WAC Circuit OutlineCircuit Operation OperationWide aspect conversion unit block diagram PB6348 Pin Function Pin function of TC9097F QFP 80 pinNames and functions of TC9097F Name FunctionVFL2 Block Diagram TC9097F system block diagramWide Aspect Conversion Circuit Failure Analysis Procedures E2PROM OK?Adjustment Method Raster Horizontal OneSection VI Dual Circuit Outline Principles of OperationScreen multi-search process System Component Diagram of Dual Unit Video/Color/Deflection Process Section OSD Sub Screen Process Section Sub screen process sectionMain/Sub Screen Superimposing Section Main/Sub screen superimposing sectionMain IC Terminal FUNCTION, Description and Block Diagram DiagramQY01 MPC1832GTQY01 mPC1832GT pin layout QY03 TC9092AF internal block diagram QY03 TC9092AF pin layout QY03 TC9092AF pin list No Pin name Pin function CKWMRD1 QY10/QY11 M518221-30ZS internal block diagram Section VII 3-DIMENSION Y/C Separator Circuit Outline Configuration Circuit DescriptionCircuit Description Terminal description PZ01 Section Viii Vertical Output Circuit Outline Theory of OperationOutput Circuit Actual CircuitSawtooth Waveform Generation Circuit OperationOutput Output stage power supply voltage Linearity Characteristic Correction Protection Circuit for V Deflection StopCharacter Correction Up-and Down-ward Extension Correction Up-and Down-ward Linearity Balance+35V Over Current Protection Circuit Theory of OperationUZ22BSD UZ11BSBRaster Position Switching Circuit KetsuSignal Section IX Horizontal Deflection Circuit OutlineHorizontal Drive Circuit Basic Operation of Horizontal DriveOn period OFF period Signal DEF/POWER PCB Horizontal Output CircuitOperation of Basic Circuit FBTDescription of the basic circuit T1~t2 T2~t3T3~t4 T4~t6Amplitude Correction Linearity Correction LINCurve Correction S Capacitor Left-right Asymmetrical Correction LIN coil Linearity coilWhite Peak Bending Correction Circuit OutlineOperation Theory EHTBlanking Low Voltage Protection Gate ProtectorHigh Voltage Generation Circuit AFCABL High Voltage DPC Circuit Regulator1. +210V 2. +35VHigh Voltage High Voltage Circuit CR-BLOCKAnode Actual FBT CR-BLOCK E HED’ RAY Protection Circuit 23 X-RAY protection circuitOver Current Protection Circuit Functions and Features Block DiagramDiode Modulator Circuit OUTActual Circuit Basic Operation and Current Path Later Half Scanning PeriodFirst Half Scanning Period Later Half of Flyback Period First Half of Scanning PeriodP.T Section XI Digital Convergence Circuit Outline Reset MemoryProm PLLPicture Adjustment Service Mode Entering/Exiting ModeInitial screen First screen Second screenSfull Key function of remote control unit ENTOperation procedure Each Screen Adjustment MethodNormal/Full Theater Wide1 Theater Wide 269.5 When CRT is Replaced When Convergence Unit is ReplacedCase Study Troubleshooting Adjusting Procedure in Replacing CRTAdjusting Procedure in Replacing Convergence Unit/Main Def Convergence Output Circuit Convergence Block Diagram Convergence Troubleshooting Chart Main Unit
Top Page Image Contents