Toshiba TW40F80 manual Audio Multiplex Demodulation Circuit

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1-3. Audio Multiplex Demodulation Circuit

The sound multiplex composite signal FM-detected in the PIF circuit enters pin 12 of HIC (hybrid IC) in passing through the separation adjustment VR RV2 and amplified. After the amplification, the signal is split into two: one en- ters a de-emphasis circuit, and only the main signal with the L-R signal and a SAP signal removed enters the matrix cir- cuit. At the same time, the other passes through various fil- ters and trap circuits, and the L-R signal is AM-demodu- lated, and the SAP is FM-demodulated.

MVUS34S

Then, both are fed to the matrix circuit. At the same time, each of the stereo pilot signal fH and the SAP pilot signal 5fH is also demodulated to obtain an identification voltage. With the identification voltage thus obtained and the user control voltage are used to control the matrix.

The audio signals obtained by demodulating the sound mul- tiplex signal develop at pin 10 and 11 of HIC and develop the terminals of 12 and 14 of the module.

MPX			TV	DAC-out1	TV	DAC-out2
Out			R-Out (SURR ON/OFF)		L-Out	(RFSW)
9	10	11	12	13	14	15

Monitor the input pin for multiplex sound IC

Stereo 0V

Other 5V


SAP		0V

Other		5V


OFF		0V

ON		9V


RF1		0V

RF2		9V

TV waveform detection	TV waveform detection
output (R)	output (L)

To AV select circuit

Fig. 2-2 Block diagram of MVUS34S

Table 2-1 Matrix for broadcasting conditions and reception mode

Note:

Of the mode selection voltages, switching voltages for STE, SAP, MONO do not output outside the module.

	Broad-	Switching	Output		OSD display

			12 pin	14 pin
	casted	mode	12 pin	14 pin	Stereo	SAP
			(R)	(L)
	Stereo	STE	R	L	•	–
		SAP	R	L	•	–
		SAP	R	L	•	–
					•
	Mono	MONO	L+R	L+R	•	–
	Mono	STE	L+R	L+R	–	–
		SAP	L+R	L+R	–	–
		MONO	L+R	L+R	–	–

	Stereo	STE	R	L	•	•
	+	SAP	SAP	SAP	•	•
	+	SAP	SAP	SAP	•	•
	SAP	MONO	L+R	L+R	•	•
	Mono	STE	L+R	L+R	–	•
	+	SAP	SAP	SAP	–	•
	+	SAP	SAP	SAP	–	•
	SAP	MONO	L+R	L+R	–	•
	SAP	MONO	L+R	L+R	–	•
						•

They are used inside the module to control the BUS.

•: Available, – : Not available

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Contents TW40F80 Contents Wide Aspect Conversion Circuit Failure Analysis Terminal FUNCTION, Description and Block DiagramSection XI Digital Convergence Circuit Section X Deflection Distortion Correction CircuitImproved Serviceability Section FeatureOutline Merits of BUS System Reduction of Parts CountChassis Model SpecificationsVideo 3 Inputs Front ViewIN-VIDEO Rear View100 Remote Control ViewStarsight Newosd FRO. Surr Chassis LayoutConstruction of Chassis Section II TUNER, IF/MTS/S. PRO Module Circuit Block Major FeaturesOutline RF AGCAudio Multiplex Demodulation Circuit A.PRO Section Audio Processor A.PRO block diagramConfiguration of the audio circuit and signal flow are given Terminal No Name POP TunerOperation of Channel Selection Circuit SDA SCL MicrocomputerMicrocomputer Terminal Function Terminal Name Function In/Out Logic Remarks Microcomputer Terminal Name and Operation LogicEEPROMQA02 On Screen FunctionSDA System Block Diagram Local key assignment Function Local KEY Detection MethodCode Function Remote Control Code AssignmentTo TV set Custom codes are 40-BFH TV set for North U.S.A Code Function OPT0 OPT1 Models HEX Optional Setting for Each ModelTest Signal Selection Entering to Service ModeService Adjustment Contents to be Confirmed by Customer Failure Diagnosis ProcedureExecuting Self Diagnosis Function Self Check Understanding Self Diagnosis IndicationClearing method of self diagnosis result TV does Not Turned on Troubleshooting ChartYES No Picture Snow Noise No Acception of KEY-INNo Indication On Screen Memory Circuit CheckSection IV DVD Switch Circuit DVD Switch Block Diagram Outline Section V WAC Circuit Outline ConfigurationCircuit Operation OperationWide aspect conversion unit block diagram PB6348 Pin function of TC9097F QFP 80 pin Pin FunctionName Function Names and functions of TC9097FVFL2 TC9097F system block diagram Block DiagramE2PROM OK? Wide Aspect Conversion Circuit Failure Analysis ProceduresRaster Horizontal One Adjustment MethodPrinciples of Operation Section VI Dual Circuit OutlineScreen multi-search process System Component Diagram of Dual Unit Video/Color/Deflection Process Section OSD Sub screen process section Sub Screen Process SectionMain/Sub screen superimposing section Main/Sub Screen Superimposing SectionDiagram Main IC Terminal FUNCTION, Description and Block DiagramQY01 MPC1832GTQY01 mPC1832GT pin layout QY03 TC9092AF internal block diagram QY03 TC9092AF pin layout CKW QY03 TC9092AF pin list No Pin name Pin functionMRD1 QY10/QY11 M518221-30ZS internal block diagram Configuration Circuit Description Section VII 3-DIMENSION Y/C Separator Circuit OutlineCircuit Description Terminal description PZ01 Theory of Operation Section Viii Vertical Output Circuit OutlineActual Circuit Output CircuitSawtooth Waveform Generation Circuit OperationOutput Output stage power supply voltage Protection Circuit for V Deflection Stop Linearity Characteristic CorrectionCharacter Correction Up-and Down-ward Extension Correction Up-and Down-ward Linearity BalanceTheory of Operation +35V Over Current Protection CircuitUZ22BSD UZ11BSBKetsu Raster Position Switching CircuitSection IX Horizontal Deflection Circuit Outline SignalHorizontal Drive Circuit Basic Operation of Horizontal DriveOn period OFF period Horizontal Output Circuit Signal DEF/POWER PCBOperation of Basic Circuit FBTT2~t3 Description of the basic circuit T1~t2T3~t4 T4~t6Linearity Correction LIN Amplitude CorrectionCurve Correction S Capacitor Linearity coil Left-right Asymmetrical Correction LIN coilOutline White Peak Bending Correction CircuitOperation Theory EHTBlanking Gate Protector Low Voltage ProtectionAFC High Voltage Generation CircuitABL High Voltage DPC Circuit Regulator2. +35V 1. +210VHigh Voltage CR-BLOCK High Voltage CircuitAnode FBT CR-BLOCK E H ActualED’ 23 X-RAY protection circuit RAY Protection CircuitOver Current Protection Circuit Block Diagram Functions and FeaturesOUT Diode Modulator CircuitActual Circuit Later Half Scanning Period Basic Operation and Current PathFirst Half Scanning Period First Half of Scanning Period Later Half of Flyback PeriodP.T Section XI Digital Convergence Circuit Outline Memory ResetProm PLLPicture Adjustment Entering/Exiting Mode Service ModeFirst screen Second screen Initial screenSfull ENT Key function of remote control unitEach Screen Adjustment Method Operation procedureNormal/Full Theater Wide1 Theater Wide 269.5 When Convergence Unit is Replaced When CRT is ReplacedCase Study Adjusting Procedure in Replacing CRT TroubleshootingAdjusting Procedure in Replacing Convergence Unit/Main Def Convergence Output Circuit Convergence Block Diagram Convergence Troubleshooting Chart Main Unit