Toshiba TW40F80 manual QY10/QY11 M518221-30ZS internal block diagram

Page 56

Dout (X8)

 

OE

RE

RSTR SRCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data - out

 

Serial

Read

Controller

 

buffer (X8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512 Word serial read register (X8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read line buffer

Read line buffer

 

 

 

 

Low-Half (X8)

High-Half (X8)

 

 

 

 

 

 

 

 

 

71Word

Sub-register (X8)

71Word Sub-register (X8)

256 (X8)

256 (X8)

 

 

256K (X8)

X

Memory

De-

Array

coder

Read/Write and refresh controller

 

 

 

 

 

256 (X8)

 

256 (X8)

 

 

 

 

 

 

 

 

 

 

 

 

 

Write line buffer

Write line buffer

 

 

 

 

 

Low-Half (X8)

High-Half (X8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512 Word serial write register (X8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data - in

 

 

 

 

 

 

 

 

 

 

Buffer (X8)

 

 

Serial

Write

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Din (X8)

 

 

IE

WE

RSTW

SWCK

Clock oscillator

VB3

Generator

Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagram

WE

1

 

Terminal name

Function

 

2

IE

 

SWCK

Serial write clock

Din0

3

 

 

4

Din1

SRCK

Serial read clock

Din2

5

 

 

 

 

 

6

Din3

WE

Write enable

Vcc

7

 

 

 

 

 

8

Din4

RE

Read enable

Din5

9

 

IE

Input enable

 

 

 

10

Din6

 

 

 

Din7

11

RSTW

OE

Output enable

 

12

RSTW

Reset write

SWCK

13

 

 

14

NC

RSTR

Reset read

NC

15

 

 

 

 

 

16

RE

Din 0 – 7

Data input

OE

 

17

 

Dout 0 – 7

Data output

 

18

Dout7

Dout6

19

 

VCC

Power supply (+5V)

 

20

Dout5

 

 

 

Dout4

21

Vss

VSS

Ground (0V)

 

22

NC

Not connected

Dout3

23

 

 

24

Dout2

 

 

Dout1

25

 

 

 

 

26

Dout0

 

 

RSTR

27

 

 

 

 

28

SRCK

 

 

28PIN ZIP

Fig. 6-10 QY10/QY11 M518221-30ZS pin layout

56

Image 56
Contents TW40F80 Contents Terminal FUNCTION, Description and Block Diagram Wide Aspect Conversion Circuit Failure AnalysisSection X Deflection Distortion Correction Circuit Section XI Digital Convergence CircuitSection Feature Improved ServiceabilityOutline Merits of BUS System Reduction of Parts CountSpecifications Chassis ModelFront View Video 3 InputsRear View IN-VIDEORemote Control View 100Chassis Layout Starsight Newosd FRO. SurrConstruction of Chassis Major Features Section II TUNER, IF/MTS/S. PRO Module Circuit BlockOutline RF AGCAudio Multiplex Demodulation Circuit A.PRO block diagram A.PRO Section Audio ProcessorConfiguration of the audio circuit and signal flow are given POP Tuner Terminal No NameOperation of Channel Selection Circuit Microcomputer SDA SCLMicrocomputer Terminal Function Microcomputer Terminal Name and Operation Logic Terminal Name Function In/Out Logic RemarksSDA On Screen FunctionEEPROMQA02 System Block Diagram Local KEY Detection Method Local key assignment FunctionTo TV set Remote Control Code AssignmentCode Function Custom codes are 40-BFH TV set for North U.S.A Code Function Optional Setting for Each Model OPT0 OPT1 Models HEXService Adjustment Entering to Service ModeTest Signal Selection Executing Self Diagnosis Function Failure Diagnosis ProcedureContents to be Confirmed by Customer Understanding Self Diagnosis Indication Self CheckClearing method of self diagnosis result YES Troubleshooting ChartTV does Not Turned on No Acception of KEY-IN No Picture Snow NoiseMemory Circuit Check No Indication On ScreenSection IV DVD Switch Circuit DVD Switch Block Diagram Outline Configuration Section V WAC Circuit OutlineCircuit Operation OperationWide aspect conversion unit block diagram PB6348 Pin Function Pin function of TC9097F QFP 80 pinNames and functions of TC9097F Name FunctionVFL2 Block Diagram TC9097F system block diagramWide Aspect Conversion Circuit Failure Analysis Procedures E2PROM OK?Adjustment Method Raster Horizontal OneScreen multi-search process Section VI Dual Circuit OutlinePrinciples of Operation System Component Diagram of Dual Unit Video/Color/Deflection Process Section OSD Sub Screen Process Section Sub screen process sectionMain/Sub Screen Superimposing Section Main/Sub screen superimposing sectionMain IC Terminal FUNCTION, Description and Block Diagram DiagramQY01 MPC1832GTQY01 mPC1832GT pin layout QY03 TC9092AF internal block diagram QY03 TC9092AF pin layout QY03 TC9092AF pin list No Pin name Pin function CKWMRD1 QY10/QY11 M518221-30ZS internal block diagram Circuit Description Section VII 3-DIMENSION Y/C Separator Circuit OutlineConfiguration Circuit Description Terminal description PZ01 Section Viii Vertical Output Circuit Outline Theory of OperationOutput Circuit Actual CircuitSawtooth Waveform Generation Circuit OperationOutput Output stage power supply voltage Linearity Characteristic Correction Protection Circuit for V Deflection StopCharacter Correction Up-and Down-ward Extension Correction Up-and Down-ward Linearity Balance+35V Over Current Protection Circuit Theory of OperationUZ22BSD UZ11BSBRaster Position Switching Circuit KetsuSignal Section IX Horizontal Deflection Circuit OutlineHorizontal Drive Circuit Basic Operation of Horizontal DriveOn period OFF period Signal DEF/POWER PCB Horizontal Output CircuitOperation of Basic Circuit FBTDescription of the basic circuit T1~t2 T2~t3T3~t4 T4~t6Curve Correction S Capacitor Amplitude CorrectionLinearity Correction LIN Left-right Asymmetrical Correction LIN coil Linearity coilWhite Peak Bending Correction Circuit OutlineOperation Theory EHTBlanking Low Voltage Protection Gate ProtectorHigh Voltage Generation Circuit AFCABL High Voltage DPC Circuit RegulatorHigh Voltage 1. +210V2. +35V Anode High Voltage CircuitCR-BLOCK ED’ ActualFBT CR-BLOCK E H RAY Protection Circuit 23 X-RAY protection circuitOver Current Protection Circuit Functions and Features Block DiagramDiode Modulator Circuit OUTActual Circuit First Half Scanning Period Basic Operation and Current PathLater Half Scanning Period P.T Later Half of Flyback PeriodFirst Half of Scanning Period Section XI Digital Convergence Circuit Outline Reset MemoryProm PLLPicture Adjustment Service Mode Entering/Exiting ModeSfull Initial screenFirst screen Second screen Key function of remote control unit ENTNormal/Full Operation procedureEach Screen Adjustment Method Theater Wide1 Theater Wide 269.5 Case Study When CRT is ReplacedWhen Convergence Unit is Replaced Adjusting Procedure in Replacing Convergence Unit/Main Def TroubleshootingAdjusting Procedure in Replacing CRT Convergence Output Circuit Convergence Block Diagram Convergence Troubleshooting Chart Main Unit