Toshiba TW40F80 Main/Sub Screen Superimposing Section, Main/Sub screen superimposing section

Page 49

4-3. Main/Sub Screen Superimposing Section

The main/sub screen superimposing section is shown in Fig. 6-4.

The sub screen Y, I and Q signals sent from the sub screen process section and the main screen Y, I and Q signals sent from the digital unit through the receive circuit and etnered pins 3, 2, and 1 of PY02 are clamped at a same electrical potential and the former are fed to pins 1, 3, 13 and the latter fed to pins 2, 5 and 12 of QY48.

The clamp circuit contains a clamp pulse waveshaping SCP at pin 4 of PY02, analog switches for ever-voltage source E, QY46 and QY47 and clamp capacitors CY230 ~ CY232, CY238 ~ CY240.

QY48 is an analog switch to feed the Y, I and Q signals for either sub screen or main screen to pins 15, 4 and 14 by the YS signal voltage fed to pins 9, 10 and 11. When the YS signal develops high, QY48 selects the signals for the sub screen and when low, QY48 selects the signals for the main screen. Consequently, the signals for both the main and sub screens are superimposed each other.

In normal mode (with only the main screen picture displayed), the YS signal voltage always goes low and the Y, I and Q signals from the digital unit are developed at pins 15, 4 and 14 of QY48.

The Y, I and Q signals for the main/sub screens superim- posed are developed at pins Y05, Y06 and Y04 of PY01 and then supplied to the receive circuit.

The Y, I and Q signals for the main/sub screens superim- posed inside the receive circuit are entered to pins 53, 51 and 52 of Q501 (TA1222N) and then fed to CRT. The video signal is processed in Q501 without distinguishing the sig- nals for main and sub screens, so the high picture quality can be obtained equally for both the screens.

From Sub screen process section

Signal reception circuit

 

Clump capacitor

 

 

QY48 MC74HC4053

 

 

Y

CY231

 

1

IY (Y IN)

 

 

 

 

 

 

 

I

CY230

 

3

IZ (I IN)

 

 

 

 

 

 

 

Q

CY232

 

13

IX (Q IN)

 

 

 

 

 

 

 

YS

 

 

11

A Y COM (Y OUT)

15

 

 

 

 

 

 

 

 

10

B Z -COM (I OUT)

4

 

PY02

Clump capacitor

9

C X-COM (Q OUT)

14

 

 

 

 

3

YD

CY239

2

OY (Y IN)

 

 

 

 

 

2

ID

 

CY240

5

OZ (I IN)

 

 

 

 

 

1

QD

 

 

 

CY238

 

 

 

 

12 OX (Q IN)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QY46

 

 

 

QY47

 

 

 

Main/Sub

picture

 

SCP

 

 

 

 

 

 

superimpose

4

TC74HC4066AF

TC74HC4066AF

 

 

 

 

 

3

 

 

 

4

3

 

 

 

4

 

 

 

 

9

Analog

8

9

Analog

8

 

 

 

 

1

SW

 

2

1

SW

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

6

13

 

 

5

6

13

 

 

 

Waveform

Clump

 

 

 

 

 

 

 

 

 

 

 

 

pulse

 

 

 

 

 

 

 

 

 

Constant voltage

 

shape

 

 

 

 

 

 

 

 

 

 

source E

 

PY01

Signal reception

circuit

 

 

YOUT

Y05

I

Y06

Q

Y04

 

 

Q501

 

 

TA1222N

 

Y

53

43

R

 

 

I

51

42

G

 

 

Q

52

41

B

 

 

To CRT

Fig. 6-4 Main/Sub screen superimposing section

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Contents TW40F80 Contents Wide Aspect Conversion Circuit Failure Analysis Terminal FUNCTION, Description and Block DiagramSection XI Digital Convergence Circuit Section X Deflection Distortion Correction CircuitImproved Serviceability Section FeatureOutline Merits of BUS System Reduction of Parts CountChassis Model SpecificationsVideo 3 Inputs Front ViewIN-VIDEO Rear View100 Remote Control ViewStarsight Newosd FRO. Surr Chassis LayoutConstruction of Chassis Section II TUNER, IF/MTS/S. PRO Module Circuit Block Major FeaturesOutline RF AGCAudio Multiplex Demodulation Circuit A.PRO Section Audio Processor A.PRO block diagramConfiguration of the audio circuit and signal flow are given Terminal No Name POP TunerOperation of Channel Selection Circuit SDA SCL MicrocomputerMicrocomputer Terminal Function Terminal Name Function In/Out Logic Remarks Microcomputer Terminal Name and Operation LogicEEPROMQA02 On Screen FunctionSDA System Block Diagram Local key assignment Function Local KEY Detection MethodCode Function Remote Control Code AssignmentTo TV set Custom codes are 40-BFH TV set for North U.S.A Code Function OPT0 OPT1 Models HEX Optional Setting for Each ModelTest Signal Selection Entering to Service ModeService Adjustment Contents to be Confirmed by Customer Failure Diagnosis ProcedureExecuting Self Diagnosis Function Self Check Understanding Self Diagnosis IndicationClearing method of self diagnosis result TV does Not Turned on Troubleshooting ChartYES No Picture Snow Noise No Acception of KEY-INNo Indication On Screen Memory Circuit CheckSection IV DVD Switch Circuit DVD Switch Block Diagram Outline Section V WAC Circuit Outline ConfigurationCircuit Operation OperationWide aspect conversion unit block diagram PB6348 Pin function of TC9097F QFP 80 pin Pin FunctionName Function Names and functions of TC9097FVFL2 TC9097F system block diagram Block DiagramE2PROM OK? Wide Aspect Conversion Circuit Failure Analysis ProceduresRaster Horizontal One Adjustment MethodPrinciples of Operation Section VI Dual Circuit OutlineScreen multi-search process System Component Diagram of Dual Unit Video/Color/Deflection Process Section OSD Sub screen process section Sub Screen Process SectionMain/Sub screen superimposing section Main/Sub Screen Superimposing SectionDiagram Main IC Terminal FUNCTION, Description and Block DiagramQY01 MPC1832GTQY01 mPC1832GT pin layout QY03 TC9092AF internal block diagram QY03 TC9092AF pin layout CKW QY03 TC9092AF pin list No Pin name Pin functionMRD1 QY10/QY11 M518221-30ZS internal block diagram Configuration Circuit Description Section VII 3-DIMENSION Y/C Separator Circuit OutlineCircuit Description Terminal description PZ01 Theory of Operation Section Viii Vertical Output Circuit OutlineActual Circuit Output CircuitSawtooth Waveform Generation Circuit OperationOutput Output stage power supply voltage Protection Circuit for V Deflection Stop Linearity Characteristic CorrectionCharacter Correction Up-and Down-ward Extension Correction Up-and Down-ward Linearity BalanceTheory of Operation +35V Over Current Protection CircuitUZ22BSD UZ11BSBKetsu Raster Position Switching CircuitSection IX Horizontal Deflection Circuit Outline SignalHorizontal Drive Circuit Basic Operation of Horizontal DriveOn period OFF period Horizontal Output Circuit Signal DEF/POWER PCBOperation of Basic Circuit FBTT2~t3 Description of the basic circuit T1~t2T3~t4 T4~t6Linearity Correction LIN Amplitude CorrectionCurve Correction S Capacitor Linearity coil Left-right Asymmetrical Correction LIN coilOutline White Peak Bending Correction CircuitOperation Theory EHTBlanking Gate Protector Low Voltage ProtectionAFC High Voltage Generation CircuitABL High Voltage DPC Circuit Regulator2. +35V 1. +210VHigh Voltage CR-BLOCK High Voltage CircuitAnode FBT CR-BLOCK E H ActualED’ 23 X-RAY protection circuit RAY Protection CircuitOver Current Protection Circuit Block Diagram Functions and FeaturesOUT Diode Modulator CircuitActual Circuit Later Half Scanning Period Basic Operation and Current PathFirst Half Scanning Period First Half of Scanning Period Later Half of Flyback PeriodP.T Section XI Digital Convergence Circuit Outline Memory ResetProm PLLPicture Adjustment Entering/Exiting Mode Service ModeFirst screen Second screen Initial screenSfull ENT Key function of remote control unitEach Screen Adjustment Method Operation procedureNormal/Full Theater Wide1 Theater Wide 269.5 When Convergence Unit is Replaced When CRT is ReplacedCase Study Adjusting Procedure in Replacing CRT TroubleshootingAdjusting Procedure in Replacing Convergence Unit/Main Def Convergence Output Circuit Convergence Block Diagram Convergence Troubleshooting Chart Main Unit
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