Toshiba TW40F80 manual Section VII 3-DIMENSION Y/C Separator Circuit Outline, Circuit Description

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SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT

1. OUTLINE

The 3D YC separation circuit uses a comb filter with a frame memory and ideally separates the Y (luminance) and color signal for still parts of a picture, thus providing a clean pic- ture without:

(1)Dot interference causing at border areas of color pic- tures.

(2)Excess color in vertical direction.

However in a moving picture, as the picture moves between the first and second frames, good separation is not obtained.

To prevent this, a motion detection is carried out in the 3D YC separation (hereafter called YCS) unit (PB6347). When a picture moving is detected a 2D YC separation using a line memory is switched in and when not detected or for a still picture 3D YC separation is switched in, thereby cor- recting defects both the systems have and performing the ideal YC separation. The motion detection accuracy and smoothness of the switching, etc. are controlled through the IIC bus.

After completion of the Y and S signal separation, a vertical contour correction is carried out for the Y signal.

2. CIRCUIT DESCRIPTION

2-1. Configuration

2-2. Circuit Description

Fig. 7-1 shows a block diagram of the YCS circuit.

(1)A video signal sent through the AV switching circuit passes the input terminal (DG) and enters the YCS unit.

(2)The video signal entered is limited in its band width in passing through an aliasing distortion elimination LPF consisting of LZ22, etc. , and then enters pin 56 of QZ01.

(3)At the same time, a fsc (3.58 MHz) signal being oscil- lated in the video signal color IC (Q501, AN1222AN) is fed to pin 28 of QZ01 and converted into a 4fsc (14.32 MHz), a drive clock frequency inside the IC.

(4)The video signal entered pin 56 of QZ01 is processed inside the IC and a luminance (Y) signal is developed at pin 48 of QZ01 and the color signal at the pin 51.

(5)The Y signal developed at pin 48 of QZ01 passes a LPF (LZ20, etc.) which eliminates the clock signal component, amplified by a 6dB amplifier QZ21, etc. and comes out from the DC terminal as the Y signal.

(6)At the same time, the color signal developed at pin 51 of QZ01 passes a LPF (LZ21, etc.) which eliminates the clock component, amplified by 6dB by QZ23, etc. and comes out from DD terminal through a buffer of QZ24 as the C signal.

The YCS unit consists of a YC separation IC (QZ01, TC9086F) which plays major roles, 2 Mbyte field memory (QZ02, QZ03), clock generation IC (QZ04, TA8667F), and peripheral circuits (LPF, AMP,emitter followers, etc.).

Of the above circuit blocks, QZ01 (TC9086F) includes an A/D converter, D/A converter, clamp circuit, 4fsc PLL cir- cuit, 1 line dot countermeasure circuit, vertical contour cor- rection logic circuit, etc. and provides a high separation with less variations.

(7)QZ04 is generating a clock signal used to read and write the digital data between QZ03 and QZ04 based on the video signal.

(QZ16 emitter: 28.6 MHz ± 0.2 MHz, adjusted by LZ25.)

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Contents TW40F80 Contents Wide Aspect Conversion Circuit Failure Analysis Terminal FUNCTION, Description and Block DiagramSection XI Digital Convergence Circuit Section X Deflection Distortion Correction CircuitImproved Serviceability Section FeatureOutline Merits of BUS System Reduction of Parts CountChassis Model SpecificationsVideo 3 Inputs Front ViewIN-VIDEO Rear View100 Remote Control ViewStarsight Newosd FRO. Surr Chassis LayoutConstruction of Chassis Section II TUNER, IF/MTS/S. PRO Module Circuit Block Major FeaturesOutline RF AGCAudio Multiplex Demodulation Circuit A.PRO Section Audio Processor A.PRO block diagramConfiguration of the audio circuit and signal flow are given Terminal No Name POP TunerOperation of Channel Selection Circuit SDA SCL MicrocomputerMicrocomputer Terminal Function Terminal Name Function In/Out Logic Remarks Microcomputer Terminal Name and Operation LogicOn Screen Function EEPROMQA02SDA System Block Diagram Local key assignment Function Local KEY Detection MethodRemote Control Code Assignment Code FunctionTo TV set Custom codes are 40-BFH TV set for North U.S.A Code Function OPT0 OPT1 Models HEX Optional Setting for Each ModelEntering to Service Mode Test Signal SelectionService Adjustment Failure Diagnosis Procedure Contents to be Confirmed by CustomerExecuting Self Diagnosis Function Self Check Understanding Self Diagnosis IndicationClearing method of self diagnosis result Troubleshooting Chart TV does Not Turned onYES No Picture Snow Noise No Acception of KEY-INNo Indication On Screen Memory Circuit CheckSection IV DVD Switch Circuit DVD Switch Block Diagram Outline Section V WAC Circuit Outline ConfigurationCircuit Operation OperationWide aspect conversion unit block diagram PB6348 Pin function of TC9097F QFP 80 pin Pin FunctionName Function Names and functions of TC9097FVFL2 TC9097F system block diagram Block DiagramE2PROM OK? Wide Aspect Conversion Circuit Failure Analysis ProceduresRaster Horizontal One Adjustment MethodSection VI Dual Circuit Outline Principles of OperationScreen multi-search process System Component Diagram of Dual Unit Video/Color/Deflection Process Section OSD Sub screen process section Sub Screen Process SectionMain/Sub screen superimposing section Main/Sub Screen Superimposing SectionDiagram Main IC Terminal FUNCTION, Description and Block DiagramQY01 MPC1832GTQY01 mPC1832GT pin layout QY03 TC9092AF internal block diagram QY03 TC9092AF pin layout CKW QY03 TC9092AF pin list No Pin name Pin functionMRD1 QY10/QY11 M518221-30ZS internal block diagram Section VII 3-DIMENSION Y/C Separator Circuit Outline Configuration Circuit DescriptionCircuit Description Terminal description PZ01 Theory of Operation Section Viii Vertical Output Circuit OutlineActual Circuit Output CircuitSawtooth Waveform Generation Circuit OperationOutput Output stage power supply voltage Protection Circuit for V Deflection Stop Linearity Characteristic CorrectionCharacter Correction Up-and Down-ward Extension Correction Up-and Down-ward Linearity BalanceTheory of Operation +35V Over Current Protection CircuitUZ22BSD UZ11BSBKetsu Raster Position Switching CircuitSection IX Horizontal Deflection Circuit Outline SignalHorizontal Drive Circuit Basic Operation of Horizontal DriveOn period OFF period Horizontal Output Circuit Signal DEF/POWER PCBOperation of Basic Circuit FBTT2~t3 Description of the basic circuit T1~t2T3~t4 T4~t6Amplitude Correction Linearity Correction LINCurve Correction S Capacitor Linearity coil Left-right Asymmetrical Correction LIN coilOutline White Peak Bending Correction CircuitOperation Theory EHTBlanking Gate Protector Low Voltage ProtectionAFC High Voltage Generation CircuitABL High Voltage DPC Circuit Regulator1. +210V 2. +35VHigh Voltage High Voltage Circuit CR-BLOCKAnode Actual FBT CR-BLOCK E HED’ 23 X-RAY protection circuit RAY Protection CircuitOver Current Protection Circuit Block Diagram Functions and FeaturesOUT Diode Modulator CircuitActual Circuit Basic Operation and Current Path Later Half Scanning PeriodFirst Half Scanning Period Later Half of Flyback Period First Half of Scanning PeriodP.T Section XI Digital Convergence Circuit Outline Memory ResetProm PLLPicture Adjustment Entering/Exiting Mode Service ModeInitial screen First screen Second screenSfull ENT Key function of remote control unitOperation procedure Each Screen Adjustment MethodNormal/Full Theater Wide1 Theater Wide 269.5 When CRT is Replaced When Convergence Unit is ReplacedCase Study Troubleshooting Adjusting Procedure in Replacing CRTAdjusting Procedure in Replacing Convergence Unit/Main Def Convergence Output Circuit Convergence Block Diagram Convergence Troubleshooting Chart Main Unit
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