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Model:   | Operation Mode: 30 fps  | 
Master Clock: 80.0 MHz, M= 12.5 nsec
Pixel Clock: 40.0 MHz, P= 25 nsec
1. Pixel Clock and Digital Data
Pixel Clock
A
Data (B)
Tcd
Tdc  | Thd  | 
Tcd: Clock to Data Ready
Tdc: Data Ready to Next Clock
Thd: Data Hold Time
Tcd = 9.0 nsec, Tdc = 16.0 nsec, Thd = 6.00 nsec.
2. Horizontal Signals  | fHD = [ 31.50 KHz]  | 
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  | tHD = [ 31.75 sec]  | 
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External HD  | 
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Internal HD | 
  | A [ 1032 P], (25.8  | s)  | 
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  | B [1270 P], (31.75 s)  | 
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LDV | C [262 P], (6.55 s)  | 
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  | D [1008 P], (25.2  | 
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  | E [1270 P], (31.75 s)  | 
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Digital Data  | 
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  | G [1088 P], (25.2  | s)  | 
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  | F [262 P], (6.55  | s)  | 
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Analog Video  | 
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H [70 P], (1.75  | s)  | 
  | J [1008 P], (25.2  | 
  | s)  | K [67 P], (1.675  | s)  | 
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  | I [192 P], (4.8  | s)  | 
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  | Operation  | |