Intel 315889-002 manual Input Voltage and Current, Input Voltages Expected

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Input Voltage and Current

4Input Voltage and Current

4.1Input Voltages - EXPECTED

The power source for the VRM/EVRD is 12 V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down.

4.2Load Transient Effects on Input Current -

EXPECTED

The design of the VRM/EVRD, including the input power delivery filter, must ensure that the maximum slew rate of the input current does not exceed 0.5 A/µs, or as specified by the separate power supply.

Note: In the case of a VRM design, the input power delivery filter may be located either on the VRM or on the baseboard. The decision for the placement of the filter will need to be coordinated between the baseboard and VRM designers.

It is recommended that the bulk input decoupling (with optional series 0.1-1 µH inductor) be placed on the baseboard by the VRM input connector and high frequency decoupling on the VRM module. Expected baseboard decoupling should be between 1000 µF to 2240 µF depending on VRM design and system power supply.

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Applications Introduction and TerminologyVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesProcessor VID signal implementation Output Voltage RequirementsVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredVIDSelect, LL1, LL0 Codes Sheet 1 Load Line / Processors SelectCC Tolerance / Die Load Line Units Select Voltage Tolerance Required VIDSelect, LL1, LL0 Codes Sheet 2Mode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Processor Power Sequencing Required Stability RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Overshoot at Turn-On or Turn-Off Required Output Filter Capacitance RequiredPolymer PWL Coefficient Quantity Value / Description560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required Output Enable Outen Required Control SignalsOuten Specifications VID 60 Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA LL0, LL1, VIDSelect Specifications Load Line Select LL0, LL1, VIDSelectVID Bit Mapping Control Signals Input Voltage and Current Input Voltages ExpectedLoad Transient Effects on Input Current Input Voltage and Current Processor Voltage Output Protection Over-Voltage Protection OVP ExpectedOver-Current Protection OCP Expected Processor Voltage Output Protection VRReady Specifications Output IndicatorsVRhot# Specifications Voltage Regulator Ready VRReady RequiredVRMpres# Specifications Load Indicator Output LoadCurrentVRMID# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM Tyco/Elcon Connector Keying VRM Connector ExpectedVRM 11.0 Connector Part Number and Vendor Name VRM Mechanical GuidelinesName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector VRM Board Temperature Required Operating Temperature ProposedNon-Operating Temperature Proposed Environmental ConditionsAltitude Proposed Safety ProposedElectrostatic Discharge Proposed Shock and Vibration ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

The Intel 315889-002 is a highly regarded processor that has made significant contributions to the computing landscape. As part of Intel's dedicated line of CPUs, this model is engineered to deliver robust performance and efficiency for a range of applications, from personal computing to enterprise solutions. Features of the Intel 315889-002 include its multi-core architecture, which allows for better multitasking capabilities. With multiple cores working simultaneously, users can run multiple applications without experiencing noticeable lag, leading to a smoother overall experience.

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