Intel 315889-002 Environmental Conditions, Operating Temperature Proposed, Humidity Proposed

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Environmental Conditions

8Environmental Conditions

The VRM/EVRD design, including materials, should meet the environmental requirements specified below.

8.1Operating Temperature - PROPOSED

The VRM/EVRD shall meet all electrical requirements when operated at the Thermal Design Current (IccTDC) over an ambient temperature range of 0ºC to +45ºC with a minimum airflow of 400 LFM (2 m/s). The volumetric airflow (Q) can be measured through a wind tunnel. For testing, the baseboard should be mounted in a duct. (A VRM should be mounted on a PCB, and then mounted in a duct.) The recommended duct cross-section, assuming the PCB is horizontal and flush with the bottom of the duct, is as follows:

•Y direction duct width (perpendicular to flow, horizontal) = 0.3 m

•Z direction duct height (perpendicular to flow, vertical) = 0.15 m

•Minimum X direction duct length in front of VRM = 6 hydraulic diameters = 1.2 m

•Minimum X direction duct length behind VRM = 2 hydraulic diameters = 0.4 m

•Velocity (v) is calculated from the volumetric flow and cross-sectional area at the inlet as:

•v = Q/(0.3 x 0.15)m2 Operating conditions shall be considered to include 10 cycles between min and max temperature at a rate of 10ºC/hour and a dwell time of 30 minutes at extremes. Temperature and airflow measurements should be made in close proximity to the VRM.

8.2VRM Board Temperature - REQUIRED

To maintain the connector within its operating temperature range, the VRM board temperature, at the connector interface, shall not exceed a temperature equal to 90ºC. At no time during the operation is the board permitted to exceed 90ºC within a distance of 2.54 mm [0.100”] from the top of connector (0.4 in. from board edge). In order not to exceed 90ºC, it is recommended that the board be constructed from 2-ounce copper cladding. Temperature and airflow measurements should be made in close proximity to the VRM.

8.3Non-Operating Temperature - PROPOSED

The VRM/EVRD shall not be damaged when exposed to temperatures between –40ºC and +70ºC. These shall be considered to include 50 cycles of minimum to maximum temperatures at 20ºC/hour with a dwell time of 20 minutes at the extremes.

8.4Humidity - PROPOSED

85% relative – operating

95% relative – non-operating

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Applications Introduction and TerminologyVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesProcessor VID signal implementation Output Voltage RequirementsVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredVIDSelect, LL1, LL0 Codes Sheet 1 Load Line / Processors SelectCC Tolerance / Die Load Line Units Select Voltage Tolerance Required VIDSelect, LL1, LL0 Codes Sheet 2Mode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Processor Power Sequencing Required Stability RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Overshoot at Turn-On or Turn-Off Required Output Filter Capacitance RequiredPolymer PWL Coefficient Quantity Value / Description560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required Output Enable Outen Required Control SignalsOuten Specifications VID 60 Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA LL0, LL1, VIDSelect Specifications Load Line Select LL0, LL1, VIDSelectVID Bit Mapping Control Signals Input Voltage and Current Input Voltages ExpectedLoad Transient Effects on Input Current Input Voltage and Current Processor Voltage Output Protection Over-Voltage Protection OVP ExpectedOver-Current Protection OCP Expected Processor Voltage Output Protection VRReady Specifications Output IndicatorsVRhot# Specifications Voltage Regulator Ready VRReady RequiredVRMpres# Specifications Load Indicator Output LoadCurrentVRMID# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM Tyco/Elcon Connector Keying VRM Connector ExpectedVRM 11.0 Connector Part Number and Vendor Name VRM Mechanical GuidelinesName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector VRM Board Temperature Required Operating Temperature ProposedNon-Operating Temperature Proposed Environmental ConditionsAltitude Proposed Safety ProposedElectrostatic Discharge Proposed Shock and Vibration ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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