Intel 315889-002 manual Voltage Tolerance Required, VIDSelect, LL1, LL0 Codes Sheet 2, Mode

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Output Voltage Requirements

Table 2-3. VID_Select, LL1, LL0 Codes (Sheet 2 of 2)

VID

VID_

LL1

LL0

 

Load Line / Processors

 

 

Table

Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

VccMAX =

VID (V) –1.25 mΩ • Icc (A)

V

3

 

 

 

 

VccMIN =

VID (V) –1.25 mΩ • Icc (A) –30 mV

 

 

 

 

 

 

mode

 

 

 

 

 

 

 

0

0

1

VccMAX =

VID (V) –1.25 mΩ • Icc (A)

V

2, 3

VccMIN =

VID (V) –1.25 mΩ • Icc (A) –30 mV

VR10.2

 

 

 

 

 

 

 

0

1

0

VccMAX =

VID (V) –1.25 mΩ • Icc (A)

V

1, 3

 

 

 

 

 

VccMIN =

VID (V) –1.25 mΩ • Icc (A) –30 mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

VccMAX =

reserved

V

3, 4

 

 

 

 

VccMIN =

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

VccMAX =

VID (V) –1.00 mΩ • Icc (A)

V

1, 3

 

 

 

 

VccMIN =

VID (V) –1.00 mΩ • Icc (A) –30 mV

 

 

 

 

 

 

mode

 

 

 

 

 

 

 

1

0

1

VccMAX =

VID (V) –1.25 mΩ • Icc (A)

V

1, 3

VccMIN =

VID (V) –1.25 mΩ • Icc (A) –30 mV

VR11.0

 

 

 

 

 

 

 

1

1

0

VccMAX =

VID (V) –1.50 mΩ • Icc (A)

V

1, 3

 

 

 

 

VccMIN =

VID (V) –1.50 mΩ • Icc (A) –30 mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

VccMAX =

VID (V) –1.25 mΩ • Icc (A)

V

1, 3

 

 

 

 

VccMIN =

VID (V) –1.25 mΩ • Icc (A) –30 mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.The Vcc values are the expected voltage measured at the processor die.

2.The Dual-Core Intel® Xeon® 7100 series / Dual-Core Intel® Xeon® processor 7000 sequence entry is required for backward compatibility for VR ‘modules’ only using the EVRD/VRM 10.2, but the VRM11.0 should be backward compatible with VRM10.2 platforms, as modular VRs can be transferred from one platform to another.

3.For VRM 11.0 mode, VRM_Pres# and VR_ID# should be held LOW for all combinations as described in Section 6.

2.3Voltage Tolerance - REQUIRED

The voltage ranges shown in Section 2.2 include the following tolerances:

Initial DC output voltage set-point error.

Output ripple and noise.

No-load offset centering error.

Current sensing and droop errors.

Component aging affect.

Full ambient temperature range and warm up.

Dynamic output changes from minimum-to-maximum and maximum-to-minimum load should be measured at the point of regulation. When measuring the response of the die voltage to dynamic loads, use the VCC_DIE_SENSE and VSS_DIE_SENSE or VCC_DIE_SENSE2 and VSS_DIE_SENSE2 pins on the processor socket with an oscilloscope set to a DC to 20-100 MHz bandwidth limit and with probes that are 1.5 pF maximum and 1 MW minimum impedance.

Variations of the input voltage.

315889-002

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Applications Introduction and TerminologyVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesProcessor VID signal implementation Output Voltage RequirementsVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredVIDSelect, LL1, LL0 Codes Sheet 1 Load Line / Processors SelectCC Tolerance / Die Load Line Units Select Voltage Tolerance Required VIDSelect, LL1, LL0 Codes Sheet 2Mode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Processor Power Sequencing Required Stability RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Overshoot at Turn-On or Turn-Off Required Output Filter Capacitance RequiredPolymer PWL Coefficient Quantity Value / Description560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required VID 60 Specifications Control SignalsOutput Enable Outen Required Outen Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA LL0, LL1, VIDSelect Specifications Load Line Select LL0, LL1, VIDSelectVID Bit Mapping Control Signals Input Voltage and Current Input Voltages ExpectedLoad Transient Effects on Input Current Input Voltage and Current Processor Voltage Output Protection Over-Voltage Protection OVP ExpectedOver-Current Protection OCP Expected Processor Voltage Output Protection Voltage Regulator Ready VRReady Required Output IndicatorsVRReady Specifications VRhot# SpecificationsVRM Present VRMpres# Expected Load Indicator Output LoadCurrentVRMpres# Specifications VRMID# SpecificationsVRM 11.0 and Platform Present Detection 315889-002 VRM Mechanical Guidelines VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM 11.0 Connector Part Number and Vendor NameName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector Environmental Conditions Operating Temperature ProposedVRM Board Temperature Required Non-Operating Temperature ProposedShock and Vibration Proposed Safety ProposedAltitude Proposed Electrostatic Discharge ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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