Intel 315889-002 manual VRM 11.0 Connector Pin Descriptions, Name Type Description

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VRM – Mechanical Guidelines

Table 7-2. VRM 11.0 Connector Pin Descriptions

Name

Type

Description

 

 

 

Load_Current

Output

Analog signal representing the output load current

 

 

 

OUTEN

Input

Output enable

 

 

 

VR_Ready

Output

Output signal indicating that the start-up sequence is complete and the

 

 

output voltage has moved to the programmed VID value.

 

 

 

VID [6:0]1

Input

Voltage ID pins used to specify the VRM output voltage

VIN+

Power

VRM Input Voltage

 

 

 

VIN

Ground

VRM Input Ground

 

 

 

VO+

Power

VRM Output Voltage

 

 

 

VO

Ground

VRM Output Ground

 

 

 

VO_SEN+

Input

Output voltage sense pins

VO_SEN–

 

 

 

 

 

VR_hot#

Output

Indicates to the system that a thermal event has been detected in the VR

 

 

 

VRM_pres#

Output

Indicates to the system that a VR10-compatible VRM is plugged into the

 

 

socket

 

 

 

VR_ID#

Output

Indicates to the system that a VR11-compatible VRM is plugged into the

 

 

socket

 

 

 

LL0, LL1

Input

Used to configure VR load line value

 

 

 

VID_Select

Input

Used to select between extended VR10 and VR11 VID tables

 

 

 

Note: VID7 bit is not routed from the PWM control IC to the VRM connector; VID7is to be held Low on the VRM board.

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315889-002

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Contents Design Guidelines 315889-002 Contents Figures Tables315889-002 Revision History Rev # Description Rev. DateRevision Project Document State Projects Covered 315889-002 Applications Introduction and TerminologyVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesProcessor VID signal implementation Output Voltage RequirementsVoltage and Current Required Time Duration s Load Line Definitions Required Icc GuidelinesVIDSelect, LL1, LL0 Codes Sheet 1 Load Line / Processors SelectCC Tolerance / Die Load Line Units Select Voltage Tolerance Required VIDSelect, LL1, LL0 Codes Sheet 2Mode Processor VCC Overshoot Required Impedance vs. Frequency ExpectedVR BW Processor Power Sequencing Required Stability RequiredImpedance ZLL Measurement Parameter Limits Timing Min Default Max Remarks Startup Sequence Timing Parameters Sheet 1Dynamic Voltage Identification D-VID Startup Sequence Timing Parameters Sheet 2Processor Transition States Overshoot at Turn-On or Turn-Off Required Output Filter Capacitance RequiredPolymer PWL Coefficient Quantity Value / Description560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Quantity Value Tolerance Temperature Motherboard Socket & PackageShut-Down Response Required Outen Specifications Control SignalsOutput Enable Outen Required VID 60 SpecificationsExtended VR 10 Voltage Identification VID Table 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mVDifferential Remote Sense VOSEN+ VR 11.0 Voltage Identification VID TableLGA LL0, LL1, VIDSelect Specifications Load Line Select LL0, LL1, VIDSelectVID Bit Mapping Control Signals Input Voltage and Current Input Voltages ExpectedLoad Transient Effects on Input Current Input Voltage and Current Processor Voltage Output Protection Over-Voltage Protection OVP ExpectedOver-Current Protection OCP Expected Processor Voltage Output Protection VRhot# Specifications Output IndicatorsVRReady Specifications Voltage Regulator Ready VRReady RequiredVRMID# Specifications Load Indicator Output LoadCurrentVRMpres# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM 11.0 Connector Part Number and Vendor Name VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM Mechanical GuidelinesVRM 11.0 Connector Pin Descriptions Name Type DescriptionMechanical Dimensions Proposed VRM 11.0 Pin AssignmentsVRM 11.0 Module and Connector Non-Operating Temperature Proposed Operating Temperature ProposedVRM Board Temperature Required Environmental ConditionsElectrostatic Discharge Proposed Safety ProposedAltitude Proposed Shock and Vibration ProposedManufacturing Considerations Lead Free Pb FreeManufacturing Considerations Zf Constant Output Impedance Design Introduction ProposedFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design Voltage Transient Tool VTT Zf Theory = FFT V t FFT I tVTT Zf Measurement Method ResultsZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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