Intel 315889-002 manual Mechanical Dimensions Proposed, VRM 11.0 Pin Assignments

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VRM – Mechanical Guidelines

Figure 7-1. VRM 11.0 Pin Assignments

KEY

KEY

KEY

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VIN

 

54

VIN+

 

 

 

 

 

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VIN

 

53

VIN+

 

 

 

 

 

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VIN

 

52

VIN+

 

 

 

 

 

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VID4

 

51

VID3

 

 

 

 

 

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VID2

 

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VID1

 

 

 

 

 

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VID0

 

49

VID5

 

 

 

 

 

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VO_SEN+

 

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VO_SEN

 

 

 

 

 

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VR_Ready

 

47

VR_hot#

 

 

 

 

 

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OUTEN

 

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LL0

 

 

 

 

 

10

Load_Current

 

45

LL1

 

 

 

 

 

11

VID6

 

44

VID_Select

 

 

 

 

 

12

VRM_pres#

 

43

VR_ID#

 

 

 

 

 

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VO

 

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VO

 

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VO

 

 

 

 

 

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VO

 

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VO

 

 

 

 

 

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VO+

 

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VO

 

 

 

 

 

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VO

 

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VO

 

 

 

 

 

25

VO+

 

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VO+

 

29

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27

VO+

 

28

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7.4Mechanical Dimensions - PROPOSED

The mechanical dimensions for the VRM 11.0 module and connector are shown in Figure 7-1.

7.4.1Gold Finger Specification

The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that is 1.50 mm ±0.2 mm [0.059” ±0.008”] wide by 6.00 mm [0.236”] minimum long and spaced 2.50 mm [0.098”] apart. Traces from the lands to the power plane should be a minimum of 0.89 mm [0.035”] wide and of a minimal length.

315889-002

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Introduction and Terminology ApplicationsVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesOutput Voltage Requirements Processor VID signal implementationVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredLoad Line / Processors Select VIDSelect, LL1, LL0 Codes Sheet 1CC Tolerance / Die Load Line Units Select VIDSelect, LL1, LL0 Codes Sheet 2 Voltage Tolerance RequiredMode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Stability Required Processor Power Sequencing RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Output Filter Capacitance Required Overshoot at Turn-On or Turn-Off RequiredPolymer PWL Quantity Value / Description Coefficient560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required VID 60 Specifications Control SignalsOutput Enable Outen Required Outen Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA Load Line Select LL0, LL1, VIDSelect LL0, LL1, VIDSelect SpecificationsVID Bit Mapping Control Signals Input Voltages Expected Input Voltage and CurrentLoad Transient Effects on Input Current Input Voltage and Current Over-Voltage Protection OVP Expected Processor Voltage Output ProtectionOver-Current Protection OCP Expected Processor Voltage Output Protection Voltage Regulator Ready VRReady Required Output IndicatorsVRReady Specifications VRhot# SpecificationsVRM Present VRMpres# Expected Load Indicator Output LoadCurrentVRMpres# Specifications VRMID# SpecificationsVRM 11.0 and Platform Present Detection 315889-002 VRM Mechanical Guidelines VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM 11.0 Connector Part Number and Vendor NameName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector Environmental Conditions Operating Temperature ProposedVRM Board Temperature Required Non-Operating Temperature ProposedShock and Vibration Proposed Safety ProposedAltitude Proposed Electrostatic Discharge ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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