Intel 315889-002 manual Load Indicator Output LoadCurrent, VRM Present VRMpres# Expected

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Output Indicators

to the FORCEPR# pin or through system management logic. Assertion of this signal will lower processor power consumption and reduce current draw through the voltage regulator, resulting in lower component temperatures. Sustained assertion of the FORCEPR# pin will cause noticeable platform performance degradation and should not occur when drawing less than the specified thermal design current for a properly designed system.

It is recommended that hysteresis be designed into the thermal sense circuit to prevent a scenario in which the VR_hot# signal is rapidly being asserted and de-asserted.

6.3Load Indicator Output (Load_Current) -

PROPOSED

The VRM/EVRD may have an output with a voltage (Load_Current) level that varies linearly with the VRM/EVRD output current. The PWM controller supplier may specify a voltage-current relationship consistent with the controller’s current sensing method. Baseboard designers may route this output to a test point for system validation.

6.4VRM Present (VRM_pres#) - EXPECTED

The VRM should have the VRM_pres# signal. This signal is an output signal used to indicate to the system that a VRM 10.x compatible module is plugged into the socket. VRM_pres# is an open-collector/drain or equivalent signal. Table 6-3shows the VRM_pres# pin specification. It is EXPECTED that the pull-up resistor will be located on the baseboard and will not be integrated into the VRM.

Table 6-3. VRM_pres# Specifications

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

IOL

Output Low Current

0

4

mA

VOH

Output High Voltage

0.8

5.5

V

VOL

Output Low Voltage

0

0.4

V

6.5VR_Identification (VR_ID#) - EXPECTED

The VRM should have the VR_ID# signal. This signal is an output signal used to indicate to the system that a VR11-compatible VRM is plugged into the socket.

VR_ID# is an open-collector/drain or equivalent signal. Table 6-4shows the VR_ID# pin specification. It is EXPECTED that the pull-up resistor will be located on the baseboard and will not be integrated into the VRM.

The VR_ID# signal combined with the VRM_pres# signal forms a two-bit VRM identification code to indicate the type of module installed in a system. Figure 6-1defines the two signal decode.

Table 6-4. VRM_ID# Specifications

 

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

 

 

IOL

Output Low Current

0

4

mA

 

VOH

Output High Voltage

0.8

5.5

V

 

VOL

Output Low Voltage

0

0.4

V

38

 

 

 

 

315889-002

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Contents Design Guidelines 315889-002 Contents Figures Tables315889-002 Revision History Rev # Description Rev. DateRevision Project Document State Projects Covered 315889-002 VRM/EVRD 11.0 Supported Platforms and Processors ApplicationsIntroduction and Terminology Guideline Categories Guideline CategoriesVoltage and Current Required Processor VID signal implementationOutput Voltage Requirements Time Duration s Load Line Definitions Required Icc GuidelinesCC Tolerance / Die Load Line Units Select VIDSelect, LL1, LL0 Codes Sheet 1Load Line / Processors Select Mode Voltage Tolerance RequiredVIDSelect, LL1, LL0 Codes Sheet 2 Processor VCC Overshoot Required Impedance vs. Frequency ExpectedVR BW Impedance ZLL Measurement Parameter Limits Processor Power Sequencing RequiredStability Required Timing Min Default Max Remarks Startup Sequence Timing Parameters Sheet 1Dynamic Voltage Identification D-VID Startup Sequence Timing Parameters Sheet 2Processor Transition States Polymer Overshoot at Turn-On or Turn-Off RequiredOutput Filter Capacitance Required PWL 560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc CoefficientQuantity Value / Description Quantity Value Tolerance Temperature Motherboard Socket & PackageShut-Down Response Required Outen Specifications Control SignalsOutput Enable Outen Required VID 60 SpecificationsExtended VR 10 Voltage Identification VID Table 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mVDifferential Remote Sense VOSEN+ VR 11.0 Voltage Identification VID TableLGA VID Bit Mapping LL0, LL1, VIDSelect SpecificationsLoad Line Select LL0, LL1, VIDSelect Control Signals Load Transient Effects on Input Current Input Voltage and CurrentInput Voltages Expected Input Voltage and Current Over-Current Protection OCP Expected Processor Voltage Output ProtectionOver-Voltage Protection OVP Expected Processor Voltage Output Protection VRhot# Specifications Output IndicatorsVRReady Specifications Voltage Regulator Ready VRReady RequiredVRMID# Specifications Load Indicator Output LoadCurrentVRMpres# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM 11.0 Connector Part Number and Vendor Name VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM Mechanical GuidelinesVRM 11.0 Connector Pin Descriptions Name Type DescriptionMechanical Dimensions Proposed VRM 11.0 Pin AssignmentsVRM 11.0 Module and Connector Non-Operating Temperature Proposed Operating Temperature ProposedVRM Board Temperature Required Environmental ConditionsElectrostatic Discharge Proposed Safety ProposedAltitude Proposed Shock and Vibration ProposedManufacturing Considerations Lead Free Pb FreeManufacturing Considerations Zf Constant Output Impedance Design Introduction ProposedFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design Voltage Transient Tool VTT Zf Theory = FFT V t FFT I tVTT Zf Measurement Method ResultsZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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