Intel 315889-002 manual Load Line Select LL0, LL1, VIDSelect, LL0, LL1, VIDSelect Specifications

Page 31

Control Signals

3.4Load Line Select (LL0, LL1, VID_Select) -

REQUIRED

The VID_Select, LL1 and LL0 control signal form a 3-bit load line selection and will used to configure the VRM/EVRD to supply the proper load line for the processors. These signals are programmed by the CPU package pin bonding. The VID_Select control signal will select the appropriate VR10 or VR11 VID table and remap the VID [6:0] pins to the appropriate DAC input. The signals are open-collector/drain or equivalent signals. Table 3-5shows the VID_Select, LL1, and LL0 pins specification and Table 3-6

shows equations in how to obtain VMAX and VMIN based on LL0, LL1, and VID_Select bit code. For VRMs a set of additional signals extent the usability of a modular solution,

refer to Figure 6-1.

It is EXPECTED that the pull-up resistors for LL0 and LL1 will be located on the baseboard and will not be integrated into the VRM. However, the pull-up resistor for VID_Select should be located on the VRM and to maintain backward compatibility to VRM 10.2 compliant platforms a pull-down resistor of 10 kΩ is also required. The pull- down resistor is required for VRMs only and not required for EVRDs. Typically, for EVRD converters, this signal will be pulled up to VTT (1.1 V/1.2 V) via a 4.7 kΩ resistor. As an option, 3.3 V with ± 5% regulation tolerance, may be used instead of VTT for VRM or EVRD converters. Pull-ups to 12 V or 5 V are not supported by the CPU package.

The VR 10 and VR 11.0 VID pins do not have the same voltage weight. See Table 3-6for the VID bit mapping.

Table 3-5. LL0, LL1, VID_Select Specifications

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

IOL

Output Low Current

0

4

mA

VIH

Input Voltage High

0.8

3.465

V

VIL

Input Voltage Low

0

0.4

V

Table 3-6. VID Bit Mapping

VR 10.x

-

VID 4

VID 3

VID 2

VID 1

VID 0

VID 5

VID 6

 

 

 

 

 

 

 

 

 

bit

800mV

400mV

200mV

100mV

50mV

25mV

12.5mV

6.25mV

weight

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VR 11.0

VID 7

VID 6

VID 5

VID 4

VID 3

VID 2

VID 1

VID 0

 

 

 

 

 

 

 

 

 

§

315889-002

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Introduction and Terminology ApplicationsVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesOutput Voltage Requirements Processor VID signal implementationVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredLoad Line / Processors Select VIDSelect, LL1, LL0 Codes Sheet 1CC Tolerance / Die Load Line Units Select VIDSelect, LL1, LL0 Codes Sheet 2 Voltage Tolerance RequiredMode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Stability Required Processor Power Sequencing RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Output Filter Capacitance Required Overshoot at Turn-On or Turn-Off RequiredPolymer PWL Quantity Value / Description Coefficient560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required VID 60 Specifications Control SignalsOutput Enable Outen Required Outen Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA Load Line Select LL0, LL1, VIDSelect LL0, LL1, VIDSelect SpecificationsVID Bit Mapping Control Signals Input Voltages Expected Input Voltage and CurrentLoad Transient Effects on Input Current Input Voltage and Current Over-Voltage Protection OVP Expected Processor Voltage Output ProtectionOver-Current Protection OCP Expected Processor Voltage Output Protection Voltage Regulator Ready VRReady Required Output IndicatorsVRReady Specifications VRhot# SpecificationsVRM Present VRMpres# Expected Load Indicator Output LoadCurrentVRMpres# Specifications VRMID# SpecificationsVRM 11.0 and Platform Present Detection 315889-002 VRM Mechanical Guidelines VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM 11.0 Connector Part Number and Vendor NameName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector Environmental Conditions Operating Temperature ProposedVRM Board Temperature Required Non-Operating Temperature ProposedShock and Vibration Proposed Safety ProposedAltitude Proposed Electrostatic Discharge ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

The Intel 315889-002 is a highly regarded processor that has made significant contributions to the computing landscape. As part of Intel's dedicated line of CPUs, this model is engineered to deliver robust performance and efficiency for a range of applications, from personal computing to enterprise solutions. Features of the Intel 315889-002 include its multi-core architecture, which allows for better multitasking capabilities. With multiple cores working simultaneously, users can run multiple applications without experiencing noticeable lag, leading to a smoother overall experience.

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Overall, the Intel 315889-002 stands out as a well-rounded processor that combines performance, efficiency, security, and versatility. Its advanced technologies and thoughtful design make it suitable for a wide variety of users, from gamers to professionals, seeking reliable and efficient computing solutions.
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