Intel 315889-002 manual Vr Bw

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Output Voltage Requirements

dependent upon the selection of the bulk capacitors, ceramic capacitors, power plane routing and the tuning of the PWM controller’s feedback network. This analysis can be done with LGA771-V2 VTT tool impedance testing or through power delivery simulation if the designer can extract the parasitic resistance and inductance of the power planes on the motherboard along with good models for the decoupling capacitors.

Measured power delivery impedance should be within the tolerance band shown in Figure 2-3. The tolerance band is defined for the VTT impedance measurement only. For load line compliance, time domain validation is required and the VR tolerance band must be met at all times. Above 500 kHz, the minimum impedance tolerance is not defined and is determined by the MLCC capacitors required to get the ESL low enough to meet the load line impedance target of the FBREAK frequency. At 700 kHz, the ZMAX tolerance drops to the load line target impedance. Any resonance point that is above the ZMAX line needs to be carefully evaluated with the time domain method by applying transient loads at that frequency and looking for VMAX or VMIN violations. Maintaining the impedance profile up to FBREAK is important to ensure the package level decoupling properly matches the motherboard impedance. After FBREAK, the impedance measurement is permitted to rise at an inductive slope. The motherboard VR designer does not need to design for frequencies over FBREAK as the Intel Microprocessor package decoupling takes over in the region above FBREAK.

Each of these design elements should be fully evaluated to create a cost optimized solution, capable of satisfying the processor requirements. Experimental procedures for measuring the Z(f) profile will be included (shortly) in the next revision of the EVRD_VRM11_0_LL_dVID LGA771_775-V2 VTT Tester-UG.pdf Test Methodology User’s Guide using the VTT. Additional background information regarding the theory of operation is provided in Appendix A.

Figure 2-3. Power Distribution Impedance vs. Frequency

Z LL Max

Ztarget = Z LL

Z LL Min

Zone 1

Zone 2

PWM Droop control

Output Filter

& compensation BW

Bulk & MLCC

 

Zone 3

 

Inductive effects

 

MLCC ESL +

 

Socket

VR BW

Hz

Fbreak

500 kHz

 

700 kHz

Notes:

1.Zone 1 is defined by the VR closed loop compensation bandwidth (VR BW) of the voltage regulator. Typically 30-40 kHz for a 300 kHz voltage regulator design

2.Zones 2 & 3 are defined by the output filter capacitors and interconnect parasitic resistance and inductance. The tolerance is relaxed over 500 kHz allowing the VR designer freedom to select output filter capacitors. The goal is to keep Z(f) below ZLL up to FBREAK (2 MHz) and as flat as practical, by selection of bulk cap values, type and quantity of MLCC capacitors. The ideal impedance would be between ZLL and ZLLMin, but this may not be achieved with standard decoupling capacitors.

315889-002

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 VRM/EVRD 11.0 Supported Platforms and Processors ApplicationsIntroduction and Terminology Guideline Categories Guideline CategoriesVoltage and Current Required Processor VID signal implementationOutput Voltage Requirements Time Duration s Icc Guidelines Load Line Definitions RequiredCC Tolerance / Die Load Line Units Select VIDSelect, LL1, LL0 Codes Sheet 1Load Line / Processors Select Mode Voltage Tolerance RequiredVIDSelect, LL1, LL0 Codes Sheet 2 Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Impedance ZLL Measurement Parameter Limits Processor Power Sequencing RequiredStability Required Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Polymer Overshoot at Turn-On or Turn-Off RequiredOutput Filter Capacitance Required PWL 560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc CoefficientQuantity Value / Description Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required Output Enable Outen Required Control SignalsOuten Specifications VID 60 Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA VID Bit Mapping LL0, LL1, VIDSelect SpecificationsLoad Line Select LL0, LL1, VIDSelect Control Signals Load Transient Effects on Input Current Input Voltage and CurrentInput Voltages Expected Input Voltage and Current Over-Current Protection OCP Expected Processor Voltage Output ProtectionOver-Voltage Protection OVP Expected Processor Voltage Output Protection VRReady Specifications Output IndicatorsVRhot# Specifications Voltage Regulator Ready VRReady RequiredVRMpres# Specifications Load Indicator Output LoadCurrentVRMID# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM Tyco/Elcon Connector Keying VRM Connector ExpectedVRM 11.0 Connector Part Number and Vendor Name VRM Mechanical GuidelinesName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector VRM Board Temperature Required Operating Temperature ProposedNon-Operating Temperature Proposed Environmental ConditionsAltitude Proposed Safety ProposedElectrostatic Discharge Proposed Shock and Vibration ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

The Intel 315889-002 is a highly regarded processor that has made significant contributions to the computing landscape. As part of Intel's dedicated line of CPUs, this model is engineered to deliver robust performance and efficiency for a range of applications, from personal computing to enterprise solutions. Features of the Intel 315889-002 include its multi-core architecture, which allows for better multitasking capabilities. With multiple cores working simultaneously, users can run multiple applications without experiencing noticeable lag, leading to a smoother overall experience.

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