Intel 315889-002 manual Startup Sequence Timing Parameters Sheet 1, Timing Min Default Max Remarks

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Output Voltage Requirements

Figure 2-4. Power-On Sequence Timing Diagram

BCLK [1:0] (for reference only)

PWM Vcc

(5V/12V)

Tf Ta

VTT

VTT_PWRGD

OUTEN

VID_SELECT Tg

(pulled up to VTT)

Tc

 

 

VBOOT=1.1V

 

Vcc_CPU

Td

Te

 

Tb

 

VR_READY

VID bits

/ BSEL[2:0]

CPU_PWGOOD (from platform, for reference only)

RESET# (for reference only)

VCCPLL

(for reference only)

VID code read by PWM at the end of Tc VID valid

Notes:

1.VTT_PWRGD can be designed to be driving directly the OUTEN input.

2.Tb and Td voltage slopes are determined by soft start logic of the PWM controller.

3.Vboot is a default power-on Vcc (Core) value. Upon detection of a valid Vtt supply, the PWM controller is to regulate to this value until the VID codes are read. The Vboot voltage is 1.1 V

4.VTT is the processor termination regulator’s output voltage and the VTT_PWRGD is the VTT regulator’s power good status indicator.

5.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

6.This specification requires that the VID signals be sampled no earlier than 10 µs after VCC (at VCC_BOOT voltage) and VTT are stable.

7.Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply is in regulation as defined by the minimum and maximum DC/AC specifications for all components being powered by it.

8.The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor. Measured between (0.3 * VTT) and (0.7 * VTT).

Table 2-5. Startup Sequence Timing Parameters (Sheet 1 of 2)

Timing

Min

Default

Max

Remarks

 

 

 

 

 

Ta =

 

 

 

If the actual timing exceeds 2ms, the

PWM Vcc & Vtt to OUTEN delay

0

2.0 ms

5.0 ms

VTT VR must be capable of

supporting full Itt surge current

time

 

 

 

 

 

 

 

requirement per Proc’s latest EMTS

 

 

 

 

 

Tb =

0.05 ms1

0.5 ms

10.0 ms

Programmable soft start ramp;

Vboot rise time

 

 

 

Measured from 10-90% of slope

 

 

 

 

 

Tc =

0.05 ms1

 

3.0 ms

 

Vboot to VID valid delay time

 

 

 

 

 

 

 

315889-002

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Contents Design Guidelines 315889-002 Contents Tables Figures315889-002 Rev # Description Rev. Date Revision HistoryRevision Project Document State Projects Covered 315889-002 Introduction and Terminology ApplicationsVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesOutput Voltage Requirements Processor VID signal implementationVoltage and Current Required Time Duration s Icc Guidelines Load Line Definitions RequiredLoad Line / Processors Select VIDSelect, LL1, LL0 Codes Sheet 1CC Tolerance / Die Load Line Units Select VIDSelect, LL1, LL0 Codes Sheet 2 Voltage Tolerance RequiredMode Impedance vs. Frequency Expected Processor VCC Overshoot RequiredVR BW Stability Required Processor Power Sequencing RequiredImpedance ZLL Measurement Parameter Limits Startup Sequence Timing Parameters Sheet 1 Timing Min Default Max RemarksStartup Sequence Timing Parameters Sheet 2 Dynamic Voltage Identification D-VIDProcessor Transition States Output Filter Capacitance Required Overshoot at Turn-On or Turn-Off RequiredPolymer PWL Quantity Value / Description Coefficient560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Motherboard Socket & Package Quantity Value Tolerance TemperatureShut-Down Response Required VID 60 Specifications Control SignalsOutput Enable Outen Required Outen Specifications400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV Extended VR 10 Voltage Identification VID TableVR 11.0 Voltage Identification VID Table Differential Remote Sense VOSEN+LGA Load Line Select LL0, LL1, VIDSelect LL0, LL1, VIDSelect SpecificationsVID Bit Mapping Control Signals Input Voltages Expected Input Voltage and CurrentLoad Transient Effects on Input Current Input Voltage and Current Over-Voltage Protection OVP Expected Processor Voltage Output ProtectionOver-Current Protection OCP Expected Processor Voltage Output Protection Voltage Regulator Ready VRReady Required Output IndicatorsVRReady Specifications VRhot# SpecificationsVRM Present VRMpres# Expected Load Indicator Output LoadCurrentVRMpres# Specifications VRMID# SpecificationsVRM 11.0 and Platform Present Detection 315889-002 VRM Mechanical Guidelines VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM 11.0 Connector Part Number and Vendor NameName Type Description VRM 11.0 Connector Pin DescriptionsVRM 11.0 Pin Assignments Mechanical Dimensions ProposedVRM 11.0 Module and Connector Environmental Conditions Operating Temperature ProposedVRM Board Temperature Required Non-Operating Temperature ProposedShock and Vibration Proposed Safety ProposedAltitude Proposed Electrostatic Discharge ProposedLead Free Pb Free Manufacturing ConsiderationsManufacturing Considerations Introduction Proposed Zf Constant Output Impedance DesignFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design = FFT V t FFT I t Voltage Transient Tool VTT Zf TheoryResults VTT Zf Measurement MethodZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

The Intel 315889-002 is a highly regarded processor that has made significant contributions to the computing landscape. As part of Intel's dedicated line of CPUs, this model is engineered to deliver robust performance and efficiency for a range of applications, from personal computing to enterprise solutions. Features of the Intel 315889-002 include its multi-core architecture, which allows for better multitasking capabilities. With multiple cores working simultaneously, users can run multiple applications without experiencing noticeable lag, leading to a smoother overall experience.

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