Intel 315889-002 manual Zf Constant Output Impedance Design

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Z(f) Constant Output Impedance Design

current was 40 A. The waveforms show the effect of capacitor depopulation on the impedance profile above 1 MHz as pairs of high frequency MLCC capacitors are removed (banks 1-9) per the bank designations depicted in Figure A-7.

Simulation comparisons are made in Figure A-8for the two extreme cases of the decoupling conditions of Figure A-7, with all MLCC plus two Al-Poly bulk capacitors in place and all cavity MLCCs plus two Al-Poly bulk capacitors removed. Simulation depicts a 6-layer distributed motherboard model. The VR model has a Type III feedback compensated switching VR (swvr) and an average model (avgvr). It can be observed from Figure A-8that the switching model measurements agrees better beyond the VR bandwidth (40 kHz) than the average model, while the average VR model performance agrees with the overall trend. Slightly lower average model impedances are also observed and other disagreements are attributed to imperfect assumptions about the parasitics of the devices and specific adaptive voltage implementation in the VR models.

Figure A-5. Photo of Motherboard Analyzed Showing High Frequency MLCC Capacitors In the Socket Cavity and Bulk Capacitors

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315889-002

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Contents Design Guidelines 315889-002 Contents Figures Tables315889-002 Revision History Rev # Description Rev. DateRevision Project Document State Projects Covered 315889-002 Applications Introduction and TerminologyVRM/EVRD 11.0 Supported Platforms and Processors Guideline Categories Guideline CategoriesProcessor VID signal implementation Output Voltage RequirementsVoltage and Current Required Time Duration s Load Line Definitions Required Icc GuidelinesVIDSelect, LL1, LL0 Codes Sheet 1 Load Line / Processors SelectCC Tolerance / Die Load Line Units Select Voltage Tolerance Required VIDSelect, LL1, LL0 Codes Sheet 2Mode Processor VCC Overshoot Required Impedance vs. Frequency ExpectedVR BW Processor Power Sequencing Required Stability RequiredImpedance ZLL Measurement Parameter Limits Timing Min Default Max Remarks Startup Sequence Timing Parameters Sheet 1Dynamic Voltage Identification D-VID Startup Sequence Timing Parameters Sheet 2Processor Transition States Overshoot at Turn-On or Turn-Off Required Output Filter Capacitance RequiredPolymer PWL Coefficient Quantity Value / Description560µF/2.5V/20%/ Oscon 22µF/6.3V/20%/ X5R /1206 Mlcc Quantity Value Tolerance Temperature Motherboard Socket & PackageShut-Down Response Required Outen Specifications Control SignalsOutput Enable Outen Required VID 60 SpecificationsExtended VR 10 Voltage Identification VID Table 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mVDifferential Remote Sense VOSEN+ VR 11.0 Voltage Identification VID TableLGA LL0, LL1, VIDSelect Specifications Load Line Select LL0, LL1, VIDSelectVID Bit Mapping Control Signals Input Voltage and Current Input Voltages ExpectedLoad Transient Effects on Input Current Input Voltage and Current Processor Voltage Output Protection Over-Voltage Protection OVP ExpectedOver-Current Protection OCP Expected Processor Voltage Output Protection VRhot# Specifications Output IndicatorsVRReady Specifications Voltage Regulator Ready VRReady RequiredVRMID# Specifications Load Indicator Output LoadCurrentVRMpres# Specifications VRM Present VRMpres# ExpectedVRM 11.0 and Platform Present Detection 315889-002 VRM 11.0 Connector Part Number and Vendor Name VRM Connector ExpectedVRM Tyco/Elcon Connector Keying VRM Mechanical GuidelinesVRM 11.0 Connector Pin Descriptions Name Type DescriptionMechanical Dimensions Proposed VRM 11.0 Pin AssignmentsVRM 11.0 Module and Connector Non-Operating Temperature Proposed Operating Temperature ProposedVRM Board Temperature Required Environmental ConditionsElectrostatic Discharge Proposed Safety ProposedAltitude Proposed Shock and Vibration ProposedManufacturing Considerations Lead Free Pb FreeManufacturing Considerations Zf Constant Output Impedance Design Introduction ProposedFigure A-2. Zf Network Plot with 1.25 mΩ Load Line Zf Constant Output Impedance Design Voltage Transient Tool VTT Zf Theory = FFT V t FFT I tVTT Zf Measurement Method ResultsZf Constant Output Impedance Design 10uF 22uF Output Decoupling Design Procedure

315889-002 specifications

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